up3_clock.hier_info

用vhdl设计实现的多功能电子钟

|UP3_CLOCK
reset => ps2:U1.resetn
reset => BCD_CLK_HRD1[3].ACLR
reset => BCD_CLK_HRD1[2].ACLR
reset => BCD_CLK_HRD1[1].ACLR
reset => BCD_CLK_HRD1[0].ACLR
reset => BCD_CLK_HRD0[3].ACLR
reset => BCD_CLK_HRD0[2].ACLR
reset => BCD_CLK_HRD0[1].ACLR
reset => BCD_CLK_HRD0[0].ACLR
reset => BCD_CLK_MIN1[3].ACLR
reset => BCD_CLK_MIN1[2].ACLR
reset => BCD_CLK_MIN1[1].ACLR
reset => BCD_CLK_MIN1[0].ACLR
reset => BCD_CLK_MIN0[3].ACLR
reset => BCD_CLK_MIN0[2].ACLR
reset => BCD_CLK_MIN0[1].ACLR
reset => BCD_CLK_MIN0[0].ACLR
reset => BCD_CLK_SEC1[3].ACLR
reset => BCD_CLK_SEC1[2].ACLR
reset => BCD_CLK_SEC1[1].ACLR
reset => BCD_CLK_SEC1[0].ACLR
reset => LCD_RW~reg0.ACLR
reset => LCD_RS~reg0.ACLR
reset => LCD_E~reg0.PRESET
reset => BCD_CLK_SEC0[3].ACLR
reset => BCD_CLK_SEC0[2].ACLR
reset => DATA_BUS_VALUE[0].ACLR
reset => DATA_BUS_VALUE[1].ACLR
reset => DATA_BUS_VALUE[2].ACLR
reset => DATA_BUS_VALUE[3].PRESET
reset => BCD_CLK_SEC0[1].ACLR
reset => DATA_BUS_VALUE[4].PRESET
reset => BCD_CLK_SEC0[0].ACLR
reset => DATA_BUS_VALUE[5].PRESET
reset => DATA_BUS_VALUE[6].ACLR
reset => DATA_BUS_VALUE[7].ACLR
reset => BCD_TSEC[0].ACLR
reset => BCD_TSEC[1].ACLR
reset => BCD_TSEC[2].ACLR
reset => BCD_TSEC[3].ACLR
reset => BCD_SECD0[0].ACLR
reset => BCD_SECD0[1].ACLR
reset => BCD_SECD0[2].ACLR
reset => BCD_SECD0[3].ACLR
reset => BCD_SECD1[0].ACLR
reset => BCD_SECD1[1].ACLR
reset => BCD_SECD1[2].ACLR
reset => BCD_SECD1[3].ACLR
reset => BCD_MIND0[0].ACLR
reset => BCD_MIND0[1].ACLR
reset => BCD_MIND0[2].ACLR
reset => BCD_MIND0[3].ACLR
reset => BCD_MIND1[0].ACLR
reset => BCD_MIND1[1].ACLR
reset => BCD_MIND1[2].ACLR
reset => BCD_MIND1[3].ACLR
reset => BCD_HRD0[0].ACLR
reset => BCD_HRD0[1].ACLR
reset => BCD_HRD0[2].ACLR
reset => BCD_HRD0[3].ACLR
reset => BCD_HRD1[0].ACLR
reset => BCD_HRD1[1].ACLR
reset => BCD_HRD1[2].ACLR
reset => BCD_HRD1[3].ACLR
reset => KEY_BCD[0].ACLR
reset => KEY_BCD[1].PRESET
reset => KEY_BCD[2].ACLR
reset => KEY_BCD[3].PRESET
reset => process8~0.IN0
reset => BCD_YEAR0[0].PRESET
reset => BCD_YEAR0[1].ACLR
reset => BCD_YEAR0[2].ACLR
reset => BCD_YEAR0[3].ACLR
reset => BCD_YEAR1[0].ACLR
reset => BCD_YEAR1[1].ACLR
reset => BCD_YEAR1[2].ACLR
reset => BCD_YEAR1[3].ACLR
reset => BCD_YEAR2[0].ACLR
reset => BCD_YEAR2[1].ACLR
reset => BCD_YEAR2[2].ACLR
reset => BCD_YEAR2[3].ACLR
reset => BCD_YEAR3[0].ACLR
reset => BCD_YEAR3[1].ACLR
reset => BCD_YEAR3[2].ACLR
reset => BCD_YEAR3[3].ACLR
reset => BCD_MON0[0].PRESET
reset => BCD_MON0[1].ACLR
reset => BCD_MON0[2].ACLR
reset => BCD_MON0[3].ACLR
reset => BCD_MON1[0].ACLR
reset => BCD_MON1[1].ACLR
reset => BCD_MON1[2].ACLR
reset => BCD_MON1[3].ACLR
reset => BCD_DAY1[0].ACLR
reset => BCD_DAY1[1].ACLR
reset => BCD_DAY1[2].ACLR
reset => BCD_DAY1[3].ACLR
reset => BCD_DAY0[0].PRESET
reset => BCD_DAY0[1].ACLR
reset => BCD_DAY0[2].ACLR
reset => BCD_DAY0[3].ACLR
reset => CLK_COUNT_400HZ~20.OUTPUTSELECT
reset => CLK_COUNT_400HZ~21.OUTPUTSELECT
reset => CLK_COUNT_400HZ~22.OUTPUTSELECT
reset => CLK_COUNT_400HZ~23.OUTPUTSELECT
reset => CLK_COUNT_400HZ~24.OUTPUTSELECT
reset => CLK_COUNT_400HZ~25.OUTPUTSELECT
reset => CLK_COUNT_400HZ~26.OUTPUTSELECT
reset => CLK_COUNT_400HZ~27.OUTPUTSELECT
reset => CLK_COUNT_400HZ~28.OUTPUTSELECT
reset => CLK_COUNT_400HZ~29.OUTPUTSELECT
reset => CLK_COUNT_400HZ~30.OUTPUTSELECT
reset => CLK_COUNT_400HZ~31.OUTPUTSELECT
reset => CLK_COUNT_400HZ~32.OUTPUTSELECT
reset => CLK_COUNT_400HZ~33.OUTPUTSELECT
reset => CLK_COUNT_400HZ~34.OUTPUTSELECT
reset => CLK_COUNT_400HZ~35.OUTPUTSELECT
reset => CLK_COUNT_400HZ~36.OUTPUTSELECT
reset => CLK_COUNT_400HZ~37.OUTPUTSELECT
reset => CLK_COUNT_400HZ~38.OUTPUTSELECT
reset => CLK_COUNT_400HZ~39.OUTPUTSELECT
reset => CLK_400HZ~1.OUTPUTSELECT
reset => RESET_LED.DATAIN
reset => WEEK1[4].ENA
reset => WEEK1[3].ENA
reset => WEEK1[2].ENA
reset => WEEK1[1].ENA
reset => WEEK1[0].ENA
reset => WEEK2[7].ENA
reset => WEEK2[6].ENA
reset => WEEK2[5].ENA
reset => WEEK2[4].ENA
reset => WEEK2[3].ENA
reset => WEEK2[2].ENA
reset => WEEK2[1].ENA
reset => WEEK2[0].ENA
reset => WEEK3[7].ENA
reset => WEEK3[6].ENA
reset => WEEK3[5].ENA
reset => WEEK3[4].ENA
reset => WEEK3[3].ENA
reset => WEEK3[2].ENA
reset => WEEK3[1].ENA
reset => WEEK3[0].ENA
reset => WEEK1[5].ENA
reset => WEEK1[6].ENA
reset => WEEK1[7].ENA
reset => TIMING_LED~reg0.ENA
reset => THE_TIME.ENA
reset => ONE_MONTH.ENA
reset => ONE_DAY.ENA
reset => CLK_COUNT_10HZ[0].ENA
reset => CLK_COUNT_10HZ[1].ENA
reset => CLK_COUNT_10HZ[2].ENA
reset => CLK_COUNT_10HZ[3].ENA
reset => CLK_COUNT_10HZ[4].ENA
reset => CLK_COUNT_10HZ[5].ENA
reset => CLK_COUNT_10HZ[6].ENA
reset => CLK_COUNT_10HZ[7].ENA
reset => NEXT_STATEWEEK~1.IN1
reset => STATE_WEEK~15.IN1
reset => next_command~5.IN1
reset => state~43.IN1
clk_48Mhz => ps2:U1.clock
clk_48Mhz => CLK_400HZ.CLK
clk_48Mhz => CLK_COUNT_400HZ[0].CLK
clk_48Mhz => CLK_COUNT_400HZ[1].CLK
clk_48Mhz => CLK_COUNT_400HZ[2].CLK
clk_48Mhz => CLK_COUNT_400HZ[3].CLK
clk_48Mhz => CLK_COUNT_400HZ[4].CLK
clk_48Mhz => CLK_COUNT_400HZ[5].CLK
clk_48Mhz => CLK_COUNT_400HZ[6].CLK
clk_48Mhz => CLK_COUNT_400HZ[7].CLK
clk_48Mhz => CLK_COUNT_400HZ[8].CLK
clk_48Mhz => CLK_COUNT_400HZ[9].CLK
clk_48Mhz => CLK_COUNT_400HZ[10].CLK
clk_48Mhz => CLK_COUNT_400HZ[11].CLK
clk_48Mhz => CLK_COUNT_400HZ[12].CLK
clk_48Mhz => CLK_COUNT_400HZ[13].CLK
clk_48Mhz => CLK_COUNT_400HZ[14].CLK
clk_48Mhz => CLK_COUNT_400HZ[15].CLK
clk_48Mhz => CLK_COUNT_400HZ[16].CLK
clk_48Mhz => CLK_COUNT_400HZ[17].CLK
clk_48Mhz => CLK_COUNT_400HZ[18].CLK
clk_48Mhz => CLK_COUNT_400HZ[19].CLK
AL2NOL => process8~0.IN1
MOD_DRT => MODIFY_STATE~0.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~1.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~2.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~3.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~4.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~5.OUTPUTSELECT
MOD_DRT => MODIFY_STATE~6.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~0.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~1.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~2.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~3.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~4.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~5.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~6.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~7.OUTPUTSELECT
MOD_DRD => MODIFY_DATE_STATE~8.OUTPUTSELECT
MOD_DRW => STATE_WEEK~0.OUTPUTSELECT
MOD_DRW => STATE_WEEK~1.OUTPUTSELECT
MOD_DRW => STATE_WEEK~2.OUTPUTSELECT
MOD_DRW => STATE_WEEK~3.OUTPUTSELECT
MOD_DRW => STATE_WEEK~4.OUTPUTSELECT
MOD_DRW => STATE_WEEK~5.OUTPUTSELECT
MOD_DRW => STATE_WEEK~6.OUTPUTSELECT
MOD_OR_SET => CHAR0~0.OUTPUTSELECT
MOD_OR_SET => CHAR0~1.OUTPUTSELECT
MOD_OR_SET => CHAR0~2.OUTPUTSELECT
MOD_OR_SET => CHAR0~3.OUTPUTSELECT
MOD_OR_SET => CHAR0~4.OUTPUTSELECT
MOD_OR_SET => CHAR0~5.OUTPUTSELECT
MOD_OR_SET => CHAR0~6.OUTPUTSELECT
MOD_OR_SET => CHAR0~7.OUTPUTSELECT
MOD_OR_SET => CHARE~0.OUTPUTSELECT
MOD_OR_SET => CHARE~1.OUTPUTSELECT
MOD_OR_SET => CHARE~2.OUTPUTSELECT
MOD_OR_SET => CHARE~3.OUTPUTSELECT
MOD_OR_SET => CHARE~4.OUTPUTSELECT
MOD_OR_SET => CHARE~5.OUTPUTSELECT
MOD_OR_SET => CHARE~6.OUTPUTSELECT
MOD_OR_SET => CHARE~7.OUTPUTSELECT
MOD_OR_SET => CHAR1~0.OUTPUTSELECT
MOD_OR_SET => CHAR1~1.OUTPUTSELECT
MOD_OR_SET => CHAR1~2.OUTPUTSELECT
MOD_OR_SET => CHAR1~3.OUTPUTSELECT
MOD_OR_SET => CHAR1~4.OUTPUTSELECT
MOD_OR_SET => CHAR1~5.OUTPUTSELECT
MOD_OR_SET => CHAR1~6.OUTPUTSELECT
MOD_OR_SET => CHAR1~7.OUTPUTSELECT
MOD_OR_SET => CHARF~0.OUTPUTSELECT
MOD_OR_SET => CHARF~1.OUTPUTSELECT
MOD_OR_SET => CHARF~2.OUTPUTSELECT
MOD_OR_SET => CHARF~3.OUTPUTSELECT
MOD_OR_SET => CHARF~4.OUTPUTSELECT
MOD_OR_SET => CHARF~5.OUTPUTSELECT
MOD_OR_SET => CHARF~6.OUTPUTSELECT
MOD_OR_SET => CHARF~7.OUTPUTSELECT
MOD_OR_SET => CHAR3~0.OUTPUTSELECT
MOD_OR_SET => CHAR3~1.OUTPUTSELECT
MOD_OR_SET => CHAR3~2.OUTPUTSELECT
MOD_OR_SET => CHAR3~3.OUTPUTSELECT
MOD_OR_SET => CHAR3~4.OUTPUTSELECT
MOD_OR_SET => CHAR3~5.OUTPUTSELECT
MOD_OR_SET => CHAR3~6.OUTPUTSELECT
MOD_OR_SET => CHAR3~7.OUTPUTSELECT
MOD_OR_SET => CHAR4B~0.OUTPUTSELECT
MOD_OR_SET => CHAR4B~1.OUTPUTSELECT
MOD_OR_SET => CHAR4B~2.OUTPUTSELECT
MOD_OR_SET => CHAR4B~3.OUTPUTSELECT
MOD_OR_SET => CHAR4B~4.OUTPUTSELECT
MOD_OR_SET => CHAR4B~5.OUTPUTSELECT
MOD_OR_SET => CHAR4B~6.OUTPUTSELECT
MOD_OR_SET => CHAR4B~7.OUTPUTSELECT
MOD_OR_SET => CHAR4~0.OUTPUTSELECT
MOD_OR_SET => CHAR4~1.OUTPUTSELECT
MOD_OR_SET => CHAR4~2.OUTPUTSELECT
MOD_OR_SET => CHAR4~3.OUTPUTSELECT
MOD_OR_SET => CHAR4~4.OUTPUTSELECT
MOD_OR_SET => CHAR4~5.OUTPUTSELECT
MOD_OR_SET => CHAR4~6.OUTPUTSELECT
MOD_OR_SET => CHAR4~7.OUTPUTSELECT
MOD_OR_SET => CHAR4C~0.OUTPUTSELECT
MOD_OR_SET => CHAR4C~1.OUTPUTSELECT
MOD_OR_SET => CHAR4C~2.OUTPUTSELECT
MOD_OR_SET => CHAR4C~3.OUTPUTSELECT
MOD_OR_SET => CHAR4C~4.OUTPUTSELECT
MOD_OR_SET => CHAR4C~5.OUTPUTSELECT
MOD_OR_SET => CHAR4C~6.OUTPUTSELECT
MOD_OR_SET => CHAR4C~7.OUTPUTSELECT
MOD_OR_SET => CHAR6~0.OUTPUTSELECT
MOD_OR_SET => CHAR6~1.OUTPUTSELECT
MOD_OR_SET => CHAR6~2.OUTPUTSELECT
MOD_OR_SET => CHAR6~3.OUTPUTSELECT
MOD_OR_SET => CHAR6~4.OUTPUTSELECT
MOD_OR_SET => CHAR6~5.OUTPUTSELECT
MOD_OR_SET => CHAR6~6.OUTPUTSELECT
MOD_OR_SET => CHAR6~7.OUTPUTSELECT
MOD_OR_SET => CHAR4E~0.OUTPUTSELECT
MOD_OR_SET => CHAR4E~1.OUTPUTSELECT
MOD_OR_SET => CHAR4E~2.OUTPUTSELECT
MOD_OR_SET => CHAR4E~3.OUTPUTSELECT
MOD_OR_SET => CHAR4E~4.OUTPUTSELECT
MOD_OR_SET => CHAR4E~5.OUTPUTSELECT
MOD_OR_SET => CHAR4E~6.OUTPUTSELECT
MOD_OR_SET => CHAR4E~7.OUTPUTSELECT
MOD_OR_SET => CHAR7~0.OUTPUTSELECT
MOD_OR_SET => CHAR7~1.OUTPUTSELECT
MOD_OR_SET => CHAR7~2.OUTPUTSELECT
MOD_OR_SET => CHAR7~3.OUTPUTSELECT
MOD_OR_SET => CHAR7~4.OUTPUTSELECT
MOD_OR_SET => CHAR7~5.OUTPUTSELECT
MOD_OR_SET => CHAR7~6.OUTPUTSELECT
MOD_OR_SET => CHAR7~7.OUTPUTSELECT
MOD_OR_SET => CHAR4F~0.OUTPUTSELECT
MOD_OR_SET => CHAR4F~1.OUTPUTSELECT
MOD_OR_SET => CHAR4F~2.OUTPUTSELECT
MOD_OR_SET => CHAR4F~3.OUTPUTSELECT
MOD_OR_SET => CHAR4F~4.OUTPUTSELECT
MOD_OR_SET => CHAR4F~5.OUTPUTSELECT
MOD_OR_SET => CHAR4F~6.OUTPUTSELECT
MOD_OR_SET => CHAR4F~7.OUTPUTSELECT
MOD_OR_SET => process3~0.IN1
MOD_OR_SET => process3~3.IN1
MOD_OR_SET => process9~0.IN1
key_data => ps2:U1.ps2_dta
key_clock => ps2:U1.ps2_clk
LCD_RS <= LCD_RS~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
HIT_LED <= ps2:U1.hit_1
TIMING_LED <= TIMING_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
RESET_LED <= reset.DB_MAX_OUTPUT_PORT_TYPE
SEC_LED <= BCD_SECD0[0].DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA_BUS[0] <= comb~0
DATA_BUS[1] <= comb~1
DATA_BUS[2] <= comb~2
DATA_BUS[3] <= comb~3
DATA_BUS[4] <= comb~4
DATA_BUS[5] <= comb~5
DATA_BUS[6] <= comb~6
DATA_BUS[7] <= comb~7


|UP3_CLOCK|ps2:U1
resetn => recdata[3].ACLR
resetn => recdata[2].ACLR
resetn => recdata[1].ACLR
resetn => recdata[0].ACLR
resetn => cntval[2].ACLR
resetn => cntval[1].ACLR
resetn => cntval[0].ACLR
resetn => leds[0].PRESET
resetn => leds[1].PRESET
resetn => leds[2].PRESET
resetn => leds[3].PRESET
resetn => shift.ACLR
resetn => leds[4].PRESET
resetn => latch.ACLR
resetn => leds[5].PRESET
resetn => err.ACLR
resetn => leds[6].PRESET
resetn => parset.PRESET
resetn => leds[7].PRESET
resetn => hit_1~reg0.ACLR
resetn => recdata[4].ACLR
resetn => recdata[5].ACLR
resetn => recdata[6].ACLR
resetn => recdata[7].ACLR
resetn => act_ps2_clk.PRESET
resetn => prv_ps2_clk.PRESET
resetn => c_state~1.IN1
clock => leds[0].CLK
clock => leds[1].CLK
clock => leds[2].CLK
clock => leds[3].CLK
clock => leds[4].CLK
clock => leds[5].CLK
clock => leds[6].CLK
clock => leds[7].CLK
clock => parset.CLK
clock => err.CLK
clock => latch.CLK
clock => shift.CLK
clock => parbit.CLK
clock => cntval[0].CLK
clock => cntval[1].CLK
clock => cntval[2].CLK
clock => recdata[0].CLK
clock => recdata[1].CLK
clock => recdata[2].CLK
clock => recdata[3].CLK
clock => recdata[4].CLK
clock => recdata[5].CLK
clock => recdata[6].CLK
clock => recdata[7].CLK
clock => act_ps2_clk.CLK
clock => prv_ps2_clk.CLK
clock => c_state~0.IN1
clk_10hz => hit_1~reg0.CLK
ps2_clk => act_ps2_clk.DATAIN
ps2_dta => PARITY_CHECK~0.IN1
ps2_dta => FSM_COMB~1.IN1
ps2_dta => FSM_COMB~0.IN0
ps2_dta => n_err~2.DATAA
ps2_dta => recdata[7].DATAIN
hit_1 <= hit_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
ascii[0] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
ascii[1] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
ascii[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
ascii[3] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
ascii[4] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
ascii[5] <= <VCC>
ascii[6] <= <GND>
ascii[7] <= <GND>