up3_clock.fit.qmsg

用vhdl设计实现的多功能电子钟

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.525 ns register register " "Info: Estimated most critical path is register to register delay of 10.525 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_YEAR1\[0\] 1 REG LAB_X22_Y9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y9; Fanout = 8; REG Node = 'BCD_YEAR1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_YEAR1[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.442 ns) 1.429 ns Mux9~94 2 COMB LAB_X23_Y7 1 " "Info: 2: + IC(0.987 ns) + CELL(0.442 ns) = 1.429 ns; Loc. = LAB_X23_Y7; Fanout = 1; COMB Node = 'Mux9~94'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.429 ns" { BCD_YEAR1[0] Mux9~94 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1075 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 2.082 ns Mux9~95 3 COMB LAB_X23_Y7 1 " "Info: 3: + IC(0.211 ns) + CELL(0.442 ns) = 2.082 ns; Loc. = LAB_X23_Y7; Fanout = 1; COMB Node = 'Mux9~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Mux9~94 Mux9~95 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1075 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 2.735 ns Mux9~93 4 COMB LAB_X23_Y7 1 " "Info: 4: + IC(0.539 ns) + CELL(0.114 ns) = 2.735 ns; Loc. = LAB_X23_Y7; Fanout = 1; COMB Node = 'Mux9~93'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Mux9~95 Mux9~93 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1075 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 3.388 ns Mux10~181 5 COMB LAB_X23_Y7 1 " "Info: 5: + IC(0.211 ns) + CELL(0.442 ns) = 3.388 ns; Loc. = LAB_X23_Y7; Fanout = 1; COMB Node = 'Mux10~181'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Mux9~93 Mux10~181 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1045 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 4.041 ns Mux10~182 6 COMB LAB_X23_Y7 2 " "Info: 6: + IC(0.539 ns) + CELL(0.114 ns) = 4.041 ns; Loc. = LAB_X23_Y7; Fanout = 2; COMB Node = 'Mux10~182'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Mux10~181 Mux10~182 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1045 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.242 ns) 5.283 ns comb_8240 7 COMB LOOP LAB_X23_Y5 22 " "Info: 7: + IC(0.000 ns) + CELL(1.242 ns) = 5.283 ns; Loc. = LAB_X23_Y5; Fanout = 22; COMB LOOP Node = 'comb_8240'" { { "Info" "ITDB_PART_OF_SCC" "comb_8240 LAB_X23_Y5 " "Info: Loc. = LAB_X23_Y5; Node \"comb_8240\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { comb_8240 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { comb_8240 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.242 ns" { Mux10~182 comb_8240 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.292 ns) 6.618 ns BCD_DAY0\[1\]~6231 8 COMB LAB_X22_Y4 1 " "Info: 8: + IC(1.043 ns) + CELL(0.292 ns) = 6.618 ns; Loc. = LAB_X22_Y4; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6231'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.335 ns" { comb_8240 BCD_DAY0[1]~6231 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 7.271 ns BCD_DAY0\[1\]~6232 9 COMB LAB_X22_Y4 1 " "Info: 9: + IC(0.361 ns) + CELL(0.292 ns) = 7.271 ns; Loc. = LAB_X22_Y4; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6232'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { BCD_DAY0[1]~6231 BCD_DAY0[1]~6232 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 7.924 ns BCD_DAY0\[1\]~6234 10 COMB LAB_X22_Y4 1 " "Info: 10: + IC(0.361 ns) + CELL(0.292 ns) = 7.924 ns; Loc. = LAB_X22_Y4; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6234'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { BCD_DAY0[1]~6232 BCD_DAY0[1]~6234 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 8.577 ns BCD_DAY0\[1\]~6235 11 COMB LAB_X22_Y4 1 " "Info: 11: + IC(0.539 ns) + CELL(0.114 ns) = 8.577 ns; Loc. = LAB_X22_Y4; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6235'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { BCD_DAY0[1]~6234 BCD_DAY0[1]~6235 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 9.230 ns BCD_DAY0\[1\]~6236 12 COMB LAB_X22_Y4 3 " "Info: 12: + IC(0.539 ns) + CELL(0.114 ns) = 9.230 ns; Loc. = LAB_X22_Y4; Fanout = 3; COMB Node = 'BCD_DAY0\[1\]~6236'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.867 ns) 10.525 ns BCD_DAY0\[1\] 13 REG LAB_X22_Y4 7 " "Info: 13: + IC(0.428 ns) + CELL(0.867 ns) = 10.525 ns; Loc. = LAB_X22_Y4; Fanout = 7; REG Node = 'BCD_DAY0\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.295 ns" { BCD_DAY0[1]~6236 BCD_DAY0[1] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.767 ns ( 45.29 % ) " "Info: Total cell delay = 4.767 ns ( 45.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.758 ns ( 54.71 % ) " "Info: Total interconnect delay = 5.758 ns ( 54.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.525 ns" { BCD_YEAR1[0] Mux9~94 Mux9~95 Mux9~93 Mux10~181 Mux10~182 comb_8240 BCD_DAY0[1]~6231 BCD_DAY0[1]~6232 BCD_DAY0[1]~6234 BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 BCD_DAY0[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 13 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 13%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[0\] a permanently enabled " "Info: Pin DATA_BUS\[0\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[1\] a permanently enabled " "Info: Pin DATA_BUS\[1\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[2\] a permanently enabled " "Info: Pin DATA_BUS\[2\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[3\] a permanently enabled " "Info: Pin DATA_BUS\[3\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[4\] a permanently enabled " "Info: Pin DATA_BUS\[4\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[5\] a permanently enabled " "Info: Pin DATA_BUS\[5\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[6\] a permanently enabled " "Info: Pin DATA_BUS\[6\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[7\] a permanently enabled " "Info: Pin DATA_BUS\[7\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 19 10:47:21 2001 " "Info: Processing ended: Tue Jun 19 10:47:21 2001" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.fit.smsg " "Info: Generated suppressed messages file E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}