up3_clock.sim.rpt

用vhdl设计实现的多功能电子钟

; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      20.06 % ;
; Total nodes checked                                 ; 1602         ;
; Total output ports checked                          ; 1675         ;
; Total output ports with complete 1/0-value coverage ; 336          ;
; Total output ports with no 1/0-value coverage       ; 1310         ;
; Total output ports with no 1-value coverage         ; 1324         ;
; Total output ports with no 0-value coverage         ; 1325         ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; Node Name                                                                      ; Output Port Name                                                               ; Output Port Type ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; |UP3_CLOCK|CLK_COUNT_400HZ~17                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~17                                                  ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~18                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~18                                                  ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~19                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~19                                                  ; out              ;
; |UP3_CLOCK|CLK_400HZ~0                                                         ; |UP3_CLOCK|CLK_400HZ~0                                                         ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~37                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~37                                                  ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~38                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~38                                                  ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~39                                                  ; |UP3_CLOCK|CLK_COUNT_400HZ~39                                                  ; out              ;
; |UP3_CLOCK|CLK_400HZ~1                                                         ; |UP3_CLOCK|CLK_400HZ~1                                                         ; out              ;
; |UP3_CLOCK|CLK_COUNT_10HZ~6                                                    ; |UP3_CLOCK|CLK_COUNT_10HZ~6                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_10HZ~7                                                    ; |UP3_CLOCK|CLK_COUNT_10HZ~7                                                    ; out              ;
; |UP3_CLOCK|CLK_10HZ~0                                                          ; |UP3_CLOCK|CLK_10HZ~0                                                          ; out              ;
; |UP3_CLOCK|COUNT_CON                                                           ; |UP3_CLOCK|COUNT_CON                                                           ; regout           ;
; |UP3_CLOCK|MODIFY_HOUR1_CON                                                    ; |UP3_CLOCK|MODIFY_HOUR1_CON                                                    ; regout           ;
; |UP3_CLOCK|WideOr0                                                             ; |UP3_CLOCK|WideOr0                                                             ; out0             ;
; |UP3_CLOCK|WideOr2                                                             ; |UP3_CLOCK|WideOr2                                                             ; out0             ;
; |UP3_CLOCK|LCD_RS~0                                                            ; |UP3_CLOCK|LCD_RS~0                                                            ; out0             ;
; |UP3_CLOCK|WideOr4                                                             ; |UP3_CLOCK|WideOr4                                                             ; out0             ;
; |UP3_CLOCK|WideOr6                                                             ; |UP3_CLOCK|WideOr6                                                             ; out0             ;
; |UP3_CLOCK|WideOr8                                                             ; |UP3_CLOCK|WideOr8                                                             ; out0             ;
; |UP3_CLOCK|WideOr11                                                            ; |UP3_CLOCK|WideOr11                                                            ; out0             ;
; |UP3_CLOCK|WideOr13                                                            ; |UP3_CLOCK|WideOr13                                                            ; out0             ;
; |UP3_CLOCK|state~0                                                             ; |UP3_CLOCK|state~0                                                             ; out              ;
; |UP3_CLOCK|state~1                                                             ; |UP3_CLOCK|state~1                                                             ; out              ;
; |UP3_CLOCK|state~2                                                             ; |UP3_CLOCK|state~2                                                             ; out              ;
; |UP3_CLOCK|state~3                                                             ; |UP3_CLOCK|state~3                                                             ; out              ;
; |UP3_CLOCK|state~4                                                             ; |UP3_CLOCK|state~4                                                             ; out              ;
; |UP3_CLOCK|state~5                                                             ; |UP3_CLOCK|state~5                                                             ; out              ;
; |UP3_CLOCK|state~6                                                             ; |UP3_CLOCK|state~6                                                             ; out              ;
; |UP3_CLOCK|state~7                                                             ; |UP3_CLOCK|state~7                                                             ; out              ;
; |UP3_CLOCK|state~8                                                             ; |UP3_CLOCK|state~8                                                             ; out              ;
; |UP3_CLOCK|state~9                                                             ; |UP3_CLOCK|state~9                                                             ; out              ;
; |UP3_CLOCK|state~10                                                            ; |UP3_CLOCK|state~10                                                            ; out              ;
; |UP3_CLOCK|state~11                                                            ; |UP3_CLOCK|state~11                                                            ; out              ;
; |UP3_CLOCK|state~12                                                            ; |UP3_CLOCK|state~12                                                            ; out              ;
; |UP3_CLOCK|state~13                                                            ; |UP3_CLOCK|state~13                                                            ; out              ;
; |UP3_CLOCK|state~15                                                            ; |UP3_CLOCK|state~15                                                            ; out              ;
; |UP3_CLOCK|state~16                                                            ; |UP3_CLOCK|state~16                                                            ; out              ;
; |UP3_CLOCK|state~17                                                            ; |UP3_CLOCK|state~17                                                            ; out              ;
; |UP3_CLOCK|state~18                                                            ; |UP3_CLOCK|state~18                                                            ; out              ;
; |UP3_CLOCK|next_command~1                                                      ; |UP3_CLOCK|next_command~1                                                      ; out0             ;
; |UP3_CLOCK|BCD_HRD1~1                                                          ; |UP3_CLOCK|BCD_HRD1~1                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~2                                                          ; |UP3_CLOCK|BCD_HRD1~2                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~3                                                          ; |UP3_CLOCK|BCD_HRD1~3                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~6                                                          ; |UP3_CLOCK|BCD_HRD1~6                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~7                                                          ; |UP3_CLOCK|BCD_HRD1~7                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~10                                                         ; |UP3_CLOCK|BCD_HRD1~10                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~11                                                         ; |UP3_CLOCK|BCD_HRD1~11                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~14                                                         ; |UP3_CLOCK|BCD_HRD1~14                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~15                                                         ; |UP3_CLOCK|BCD_HRD1~15                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~18                                                         ; |UP3_CLOCK|BCD_HRD1~18                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~19                                                         ; |UP3_CLOCK|BCD_HRD1~19                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~22                                                         ; |UP3_CLOCK|BCD_HRD1~22                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~23                                                         ; |UP3_CLOCK|BCD_HRD1~23                                                         ; out              ;
; |UP3_CLOCK|BCD_TSEC~1                                                          ; |UP3_CLOCK|BCD_TSEC~1                                                          ; out              ;
; |UP3_CLOCK|BCD_TSEC~2                                                          ; |UP3_CLOCK|BCD_TSEC~2                                                          ; out              ;
; |UP3_CLOCK|BCD_TSEC~3                                                          ; |UP3_CLOCK|BCD_TSEC~3                                                          ; out              ;
; |UP3_CLOCK|BCD_HRD1~26                                                         ; |UP3_CLOCK|BCD_HRD1~26                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~27                                                         ; |UP3_CLOCK|BCD_HRD1~27                                                         ; out              ;
; |UP3_CLOCK|BCD_HRD1~30                                                         ; |UP3_CLOCK|BCD_HRD1~30                                                         ; out              ;