__projnav.log

verilog示例程序

(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.380ns (Maximum Frequency: 80.775MHz)
   Minimum input arrival time before clock: 8.136ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uart_top.vhd
Scanning    UART_PACKAGE.vhd
Scanning    uart_top.vhd
Writing uart_top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/UART/UART_PACKAGE.vhd in Library work.
Architecture uart_package of Entity uart_package is up to date.
Compiling vhdl file D:/UART/baudrate_generator.vhd in Library work.
Architecture baudrate_generator of Entity baudrate_generator is up to date.
Compiling vhdl file D:/UART/switch_bus.vhd in Library work.
Architecture switch_bus of Entity switch_bus is up to date.
Compiling vhdl file D:/UART/uart_core.vhd in Library work.
Architecture uart_core of Entity uart_core is up to date.
Compiling vhdl file D:/UART/counter.vhd in Library work.
Architecture counter of Entity counter is up to date.
Compiling vhdl file D:/UART/switch.vhd in Library work.
Architecture switch of Entity switch is up to date.
Compiling vhdl file D:/UART/detector.vhd in Library work.
Architecture detector of Entity detector is up to date.
Compiling vhdl file D:/UART/parity_verifier.vhd in Library work.
Architecture parity_verifier of Entity parity_verifier is up to date.
Compiling vhdl file D:/UART/shift_register.vhd in Library work.
Architecture shift_register of Entity shift_register is up to date.
Compiling vhdl file D:/UART/uart_top.vhd in Library work.
Entity <uart_top> (Architecture <uart_top>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <uart_top> (Architecture <uart_top>).
Entity <uart_top> analyzed. Unit <uart_top> generated.

Analyzing generic Entity <baudrate_generator> (Architecture <baudrate_generator>).
	full_pulse_count = 5208
	rise_pulse_count = 2604
Entity <baudrate_generator> analyzed. Unit <baudrate_generator> generated.

Analyzing generic Entity <switch_bus> (Architecture <switch_bus>).
	bus_width = 8
Entity <switch_bus> analyzed. Unit <switch_bus> generated.

Analyzing generic Entity <uart_core> (Architecture <uart_core>).
	data_bit = 8
	parity_rule = 2
	total_bit = 10
ERROR:Xst:792 - D:/UART/uart_core.vhd line 253: Index 10 is not in range of signal <send_buf>.
--> 

Total memory usage is 42428 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uart_top.vhd
Scanning    UART_PACKAGE.vhd
Scanning    uart_top.vhd
Writing uart_top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uart_top.vhd
Scanning    UART_PACKAGE.vhd
Scanning    uart_top.vhd
Writing uart_top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uart_top.vhd
Scanning    UART_PACKAGE.vhd
Scanning    uart_top.vhd
Writing uart_top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/UART/UART_PACKAGE.vhd in Library work.
Architecture uart_package of Entity uart_package is up to date.
Compiling vhdl file D:/UART/baudrate_generator.vhd in Library work.
Architecture baudrate_generator of Entity baudrate_generator is up to date.
Compiling vhdl file D:/UART/switch_bus.vhd in Library work.
Architecture switch_bus of Entity switch_bus is up to date.
Compiling vhdl file D:/UART/uart_core.vhd in Library work.
Architecture uart_core of Entity uart_core is up to date.
Compiling vhdl file D:/UART/counter.vhd in Library work.
Architecture counter of Entity counter is up to date.
Compiling vhdl file D:/UART/switch.vhd in Library work.
Architecture switch of Entity switch is up to date.
Compiling vhdl file D:/UART/detector.vhd in Library work.
Architecture detector of Entity detector is up to date.
Compiling vhdl file D:/UART/parity_verifier.vhd in Library work.
Architecture parity_verifier of Entity parity_verifier is up to date.
Compiling vhdl file D:/UART/shift_register.vhd in Library work.
Architecture shift_register of Entity shift_register is up to date.
Compiling vhdl file D:/UART/uart_top.vhd in Library work.
Entity <uart_top> (Architecture <uart_top>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <uart_top> (Architecture <uart_top>).
Entity <uart_top> analyzed. Unit <uart_top> generated.

Analyzing generic Entity <baudrate_generator> (Architecture <baudrate_generator>).
	full_pulse_count = 5208
	rise_pulse_count = 2604
Entity <baudrate_generator> analyzed. Unit <baudrate_generator> generated.

Analyzing generic Entity <switch_bus> (Architecture <switch_bus>).
	bus_width = 8
Entity <switch_bus> analyzed. Unit <switch_bus> generated.

Analyzing generic Entity <uart_core> (Architecture <uart_core>).
	data_bit = 8
	parity_rule = 2
	total_bit = 11
Entity <uart_core> analyzed. Unit <uart_core> generated.

Analyzing generic Entity <counter> (Architecture <counter>).
	max_count = 10
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <switch> (Architecture <switch>).
Entity <switch> analyzed. Unit <switch> generated.

Analyzing Entity <detector> (Architecture <detector>).
Entity <detector> analyzed. Unit <detector> generated.

Analyzing generic Entity <parity_verifier> (Architecture <parity_verifier>).
	data_length = 8
	parity_rule = 2
Entity <parity_verifier> analyzed. Unit <parity_verifier> generated.

Analyzing generic Entity <shift_register> (Architecture <shift_register>).
	total_bit = 11
Entity <shift_register> analyzed. Unit <shift_register> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <shift_register>.
    Related source file is D:/UART/shift_register.vhd.
    Found 1-bit register for signal <dout>.
    Found 11-bit register for signal <shift_regs>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <shift_register> synthesized.


Synthesizing Unit <parity_verifier>.
    Related source file is D:/UART/parity_verifier.vhd.
    Found 1-bit xor8 for signal <$n0000> created at line 25.
    Summary:
	inferred   1 Xor(s).
Unit <parity_verifier> synthesized.


Synthesizing Unit <detector>.
    Related source file is D:/UART/detector.vhd.
    Found 1-bit register for signal <new_data>.
    Found 1-bit register for signal <state<0>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <detector> synthesized.


Synthesizing Unit <switch>.
    Related source file is D:/UART/switch.vhd.
    Found 1 1-bit 2-to-1 multiplexers.
Unit <switch> synthesized.


Synthesizing Unit <counter>.
    Related source file is D:/UART/counter.vhd.
    Found 1-bit register for signal <overflow>.
    Found 32-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <counter> synthesized.


Synthesizing Unit <uart_core>.
    Related source file is D:/UART/uart_core.vhd.
WARNING:Xst:646 - Signal <send_buf<0>> is assigned but never used.
WARNING:Xst:646 - Signal <send_buf<10>> is assigned but never used.
    Register <sel_pv> equivalent to <sel_si> has been removed
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 3                                              |
    | Outputs            | 11                                             |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <recv_bus>.
    Found 1-bit register for signal <recv>.
    Found 1-bit register for signal <sel_out>.
    Found 1-bit register for signal <reset_dt>.
    Found 1-bit register for signal <sel_si>.
    Found 1-bit register for signal <sel_clk>.
    Found 1-bit register for signal <error>.
    Found 1-bit register for signal <send_over>.
    Found 1-bit register for signal <ce_parts>.
    Found 1-bit register for signal <reset_parts>.
    Found 4-bit adder for signal <$n0034> created at line 158.
    Found 1-bit xor2 for signal <$n0042> created at line 220.
    Found 4-bit register for signal <si_count>.
WARNING:Xst:647 - Input <regs<10>> is never used.
WARNING:Xst:647 - Input <regs<9>> is never used.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  21 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <uart_core> synthesized.


Synthesizing Unit <switch_bus>.
    Related source file is D:/UART/switch_bus.vhd.
    Found 8 1-bit 2-to-1 multiplexers.
Unit <switch_bus> synthesized.


Synthesizing Unit <baudrate_generator>.
    Related source file is D:/UART/baudrate_generator.vhd.
    Found 1-bit register for signal <indicator>.
    Found 1-bit register for signal <bg_out>.
    Found 16-bit adder for signal <$n0006> created at line 56.
    Found 16-bit register for signal <clk_count>.
    Found 17 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <baudrate_generator> synthesized.


Synthesizing Unit <uart_top>.
    Related source file is D:/UART/uart_top.vhd.
WARNING:Xst:646 - Signal <vcc> is assigned but never used.
Unit <uart_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 29
  1-bit register                   : 26
  8-bit register                   : 1
  4-bit register                   : 1
  16-bit register                  : 1
# Counters                         : 1
  32-bit up counter                : 1
# Multiplexers                     : 7
  2-to-1 multiplexer               : 7
# Adders/Subtractors               : 2
  4-bit adder                      : 1
  16-bit adder                     : 1
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor8                       : 1

=========================================================================

Optimizing FSM <FSM_0> with One-Hot encoding and d flip-flops.
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "E:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <uart_top> ...

Optimizing unit <uart_core> ...

Optimizing unit <counter> ...

Optimizing unit <baudrate_generator> ...

Mapping all equations...
Loading device for application Xst from file '2s15.nph' in environment E:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart_top, actual ratio is 52.
FlipFlop u_core_recv_bus_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop u_core_recv_bus_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s15cs144-6 

 Number of Slices:                      94  out of    192    48%  
 Number of Slice Flip Flops:           100  out of    384    26%  
 Number of 4 input LUTs:               171  out of    384    44%  
 Number of bonded IOBs:                 23  out of     90    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 55    |
u_srclkswitch_mmux_dout_result1:o  | NONE(*)(u_sr_shift_regs_3)| 12    |
u_counterclkswitch_mmux_dout_result1:o| NONE(*)(u_counter_overflow)| 33    |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.