parity_verifier.vhd

verilog示例程序

-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;

-- 实体声明
entity parity_verifier is
	-- 类属参数
	generic (
	DATA_LENGTH : integer := 8;
	PARITY_RULE : PARITY := NONE );
	-- 端口
	port (
	source : in std_logic_vector(DATA_LENGTH-1 downto 0);
	parity : out std_logic );
end parity_verifier;

--}} End of automatically maintained section
-- 结构体
architecture parity_verifier of parity_verifier is
begin

	-- enter your statements here --
	-- 按照校验规则计算校验位
	with PARITY_RULE select 
	parity <= 	MultiXOR(source) when ODD, 				-- 奇校验
				( not MultiXOR(source) ) when EVEN,		-- 偶校验
				'1' when others; 

end parity_verifier;