led.map.qmsg

是vhdl语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 11:20:53 2008 " "Info: Processing started: Wed Jul 02 11:20:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led -c led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trans.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file trans.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 trans-trans_arc " "Info: Found design unit 1: trans-trans_arc" {  } { { "trans.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/trans.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 trans " "Info: Found entity 1: trans" {  } { { "trans.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/trans.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-count_arc " "Info: Found design unit 1: count-count_arc" {  } { { "count.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/count.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "count.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/count.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file led.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.bdf" "" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-div_arc " "Info: Found design unit 1: div-div_arc" {  } { { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led " "Info: Elaborating entity \"led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count count:inst " "Info: Elaborating entity \"count\" for hierarchy \"count:inst\"" {  } { { "led.bdf" "inst" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 384 232 328 480 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "en count.vhd(26) " "Warning (10492): VHDL Process Statement warning at count.vhd(26): signal \"en\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "count.vhd" "" { Text "D:/altera/72/quartus/work/counter_clk/count.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst2 " "Info: Elaborating entity \"div\" for hierarchy \"div:inst2\"" {  } { { "led.bdf" "inst2" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 264 128 224 360 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans trans:inst1 " "Info: Elaborating entity \"trans\" for hierarchy \"trans:inst1\"" {  } { { "led.bdf" "inst1" { Schematic "D:/altera/72/quartus/work/counter_clk/led.bdf" { { 376 504 600 504 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}