trans.vhd

来自「是vhdl语言」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity trans is 
port( a,b,c,d: in std_logic;
      qout: out std_logic_vector (7 downto 0)
      );
end trans;

architecture trans_arc of trans is
signal indata: std_logic_vector (3 downto 0);
begin
indata<=d&c&b&a;
process (indata)
begin 
    case indata is
      when "0000"=>qout<="00000011";
      when "0001"=>qout<="10011111";
      when "0010"=>qout<="00100101";
      when "0011"=>qout<="00001101";
      when "0100"=>qout<="10011001";
      when "0101"=>qout<="01001001";
      when "0110"=>qout<="01000001";
      when "0111"=>qout<="00011111";
      when "1000"=>qout<="00000001";
      when "1001"=>qout<="00001001";
      when others=>qout<="XXXXXXXX";
    end case;
end process;
end trans_arc;