📄 tdmddc.mdl
字号:
LocPin "any"
cst "0"
modulename "cic_ieop"
ppat "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "cic_ierr"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [535, 322, 600, 338]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "cic_ierr"
ppat "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "cic_isop"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [535, 357, 600, 373]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "cic_isop"
ppat "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "cic_ival"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [535, 392, 600, 408]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "cic_ival"
ppat "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "cic_rstn"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [220, 462, 285, 478]
ForegroundColor "red"
SourceBlock "allblocks_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "cic_rstn"
ppat "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "cic_v6_1"
Ports [8, 7]
Position [625, 207, 840, 488]
BackgroundColor "lightBlue"
DropShadow on
SourceBlock "MegaCoreAltr/cic_v6_1"
SourceType "HDLEntity AlteraBlockSet"
altr_type "altr_megacore"
flow_dir "C:\\altera\\61\\ip\\cic\\lib\\../../common/ip_t"
"oolbench/v1.3.0/bin"
core_dir "C:\\altera\\61\\ip\\cic\\lib\\ip_toolbench"
launch_params "-parameterization.megawizard2:1 -hide_splash -"
"parameterization.activate_atstartup:1 -hide_iptb -parameterization.window_loc"
"ation:center"
core_name "cic"
core_version "6.1"
vofile "DSPBuilder_TDMDDC\\cic_v6_1.vo"
xmlmapfile "C:\\altera\\61\\DSPBuilder\\Altlib\\SimgenCMap."
"xml"
wizard "cic"
NewVariation off
VhdlVariationName "cic_v6_1.vhd"
VhdlVariationDate "07-Dec-2006 22:20:12"
n_input_port "8"
n_output_port "7"
n_clocks "1"
array_input "clken in_data in_endofpacket in_error in_starto"
"fpacket in_valid out_ready reset_n "
array_output "in_ready out_channel out_data out_endofpacket o"
"ut_error out_startofpacket out_valid "
array_clocks "clk "
clockname "clk"
inptbwl "1 8 1 2 1 1 1 1 "
inptbwr " 0 0 0 0 0 0 0 0"
inptype "bububbbb"
outptbwl "1 1 16 1 2 1 1 "
outptbwr "0 0 0 0 0 0 0"
outptype "bbububb"
dspbuilder_path "C:\\altera\\61\\DSPBuilder\\Altlib"
HDLInputPortsMappingAltera "clken.1.0.b, in_data.8.0.u, in_endofpacket.1"
".0.b, in_error.2.0.u, in_startofpacket.1.0.b, in_valid.1.0.b, out_ready.1.0.b"
", reset_n.1.0.b"
HDLOutputPortsMappingAltera "in_ready.1.0.b, out_channel.1.0.b, out_data"
".16.0.u, out_endofpacket.1.0.b, out_error.2.0.u, out_startofpacket.1.0.b, out"
"_valid.1.0.b"
HDLImplicitPortsMappingAltera "clk.clock"
HDLParameterMappingAltera "NOHDLPARAMETER"
HDLLibraryInformationAltera "ADD_COMPONENT_SECTION"
HDLComponentNameAltera "cic_v6_1"
HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_TDMDDC/cic_v6_1_add."
"tcl\";"
Port {
PortNumber 1
Name "inready"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "outchan"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "dout"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 4
Name "ciceop"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 5
Name "outerr"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 6
Name "cicsop"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 7
Name "outvalid"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType SubSystem
Name "data source"
Ports [2, 4]
Position [235, 257, 325, 408]
ForegroundColor "cyan"
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
Port {
PortNumber 4
Name "invalid"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
System {
Name "data source"
Location [0, 84, 1268, 998]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "out_ready"
Position [200, 118, 230, 132]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "resetn"
Position [145, 228, 175, 242]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [405, 105, 460, 145]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "1"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem"
Ports [1, 3, 1]
Position [225, 189, 400, 281]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Enabled\nSubsystem"
Location [2, 84, 1270, 996]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "reset_n"
Position [120, 443, 150, 457]
IconDisplay "Port number"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [955, 402, 985, 428]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "1"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [915, 432, 945, 458]
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "1"
ic_detail off
dif_ic_for_ch off
dif_ic_for_dly off
ic "0"
reset_popup "None"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [205, 225, 265, 255]
Expr "floor(2^3*u)"
}
Block {
BlockType Fcn
Name "Fcn4"
Position [175, 555, 235, 585]
Expr "floor(2^3*u)"
}
Block {
BlockType Sin
Name "Initial Sine Wave2"
Ports [0, 1]
Position [385, 360, 415, 390]
SineType "Sample based"
Amplitude "2^6 -1"
Samples "40"
SampleTime "clock1"
}
Block {
BlockType Sin
Name "Initial Sine Wave3"
Ports [0, 1]
Position [355, 690, 385, 720]
SineType "Sample based"
Amplitude "2^6 -1"
Samples "40"
Offset "20"
SampleTime "clock1"
}
Block {
BlockType Reference
Name "NOT2"
Ports [1, 1]
Position [190, 442, 230, 458]
SourceBlock "allblocks_alteradspbuilder/Logical\nBit"
" Operator"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "1"
SIGNALCOMPILER_PARAMS "Inputs;1;Operator;NOT;"
}
Block {
BlockType Reference
Name "NOT3"
Ports [1, 1]
Position [865, 407, 905, 423]
SourceBlock "allblocks_alteradspbuilder/Logical\nBit"
" Operator"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "1"
SIGNALCOMPILER_PARAMS "Inputs;1;Operator;NOT;"
}
Block {
BlockType Step
Name "Noise Inject2"
Position [280, 315, 310, 345]
Time "2000*clock1"
SampleTime "clock1"
}
Block {
BlockType Step
Name "Noise Inject3"
Position [260, 635, 290, 665]
Time "2000*clock1"
SampleTime "clock1"
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [350, 296, 395, 329]
RndMeth "Floor"
}
Block {
BlockType Product
Name "Product3"
Ports [2, 1]
Position [320, 626, 365, 659]
RndMeth "Floor"
}
Block {
BlockType RandomNumber
Name "Random\nNumber2"
Position [150, 225, 180, 255]
Variance "8"
SampleTime "clock1"
}
Block {
BlockType RandomNumber
Name "Random\nNumber3"
Position [120, 555, 150, 585]
Variance "8"
SampleTime "clock1"
}
Block {
BlockType Sin
Name "Sine Wave3"
Ports [0, 1]
Position [225, 290, 255, 320]
SineTy⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -