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📄 tdmddc.mdl

📁 Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
💻 MDL
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	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "in_sop"
	  ppat			  "d:\\dspbuilder\\Altlib\\DSPBuilder_allblock"
"s_alteradspbuilder"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Input Port;bwl;1;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "in_valid"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [100, 522, 165, 538]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "in_valid"
	  ppat			  "d:\\dspbuilder\\Altlib\\DSPBuilder_allblock"
"s_alteradspbuilder"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Input Port;bwl;1;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_data"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [540, 412, 605, 428]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "16"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Output Port;bwl"
";16;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_eop"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [520, 672, 585, 688]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Output Port;bwl;1;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_ready"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [95, 482, 160, 498]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "out_ready"
	  ppat			  "d:\\dspbuilder\\Altlib\\DSPBuilder_allblock"
"s_alteradspbuilder"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Input Port;bwl;1;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_sop"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [535, 597, 600, 613]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Output Port;bwl;1;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "out_valid"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [550, 522, 615, 538]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Output Port;bwl;1;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Outport
	  Name			  "In_ready"
	  Position		  [650, 483, 680, 497]
	  ForegroundColor	  "blue"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_valid"
	  Position		  [640, 523, 670, 537]
	  ForegroundColor	  "blue"
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_data[15:0]"
	  Position		  [630, 413, 660, 427]
	  ForegroundColor	  "blue"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_sop"
	  Position		  [625, 598, 655, 612]
	  ForegroundColor	  "blue"
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out_eop"
	  Position		  [610, 673, 640, 687]
	  ForegroundColor	  "blue"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In_data[34:0]"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "in_data"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Out_ready"
	  SrcPort		  1
	  DstBlock		  "out_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_valid"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "in_valid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_sop"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "in_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In_eop"
	  SrcPort		  1
	  DstBlock		  "in_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_ready"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "In_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_valid"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Out_valid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_sop"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Out_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_eop"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Out_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_data"
	  SrcPort		  1
	  DstBlock		  "Saturate"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_data"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Out_data[15:0]"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Saturate"
	  SrcPort		  1
	  DstBlock		  "Round"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Round"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "out_data"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "out_ready"
	  SrcPort		  1
	  DstBlock		  "in_ready"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_sop"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "out_sop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_eop"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "out_eop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_valid"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "out_valid"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [1309, 108, 1378, 155]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix II"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    on
      JTAGCable		      "USB-Blaster [USB-0]"
      dspb_ver		      "6.1"
    }
    Block {
      BlockType		      Step
      Name		      "Step"
      Position		      [130, 355, 160, 385]
      Time		      "5*clock1"
      SampleTime	      "clock1"
      ZeroCross		      off
    }
    Block {
      BlockType		      Terminator
      Name		      "Terminator"
      Position		      [870, 260, 890, 280]
    }
    Block {
      BlockType		      Terminator
      Name		      "Terminator1"
      Position		      [1250, 340, 1270, 360]
    }
    Block {
      BlockType		      Terminator
      Name		      "Terminator2"
      Position		      [1240, 460, 1260, 480]
    }
    Block {
      BlockType		      Reference
      Name		      "cic_clken"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [540, 217, 605, 233]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "cic_clken"
      ppat		      "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "cic_din"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [540, 252, 605, 268]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "cic_din"
      ppat		      "C:\\DesignExample\\DDC_CIC_Comp\\DDC_CIC_Comp_d"
"raft\\DSPBuilder_TDMDDC"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Input Port;bwl;8;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "cic_ieop"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [540, 287, 605, 303]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
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