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📄 tdmddc.mdl

📁 Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
💻 MDL
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      }
    }
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      SourceType	      "Downsample"
      N			      "2"
      phase		      "0"
      ic		      "0"
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	Name			"I_in"
	RTWStorageClass		"Auto"
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    Block {
      BlockType		      From
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      RTWMemSecDataParameters "Inherit from model"
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      XIncr		      "1.0"
      XLabel		      "Samples"
      YUnits		      "dB"
      YMin		      "14.4630814890581"
      YMax		      "51.0362810601632"
      YLabel		      "Magnitude-squared, dB"
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      SystemSampleTime	      "-1"
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      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      ScopeProperties	      on
      Domain		      "Frequency"
      HorizSpan		      "1"
      UseBuffer		      on
      BufferSize	      "128"
      Overlap		      "64"
      inpFftLenInherit	      on
      FFTlength		      "1024"
      numAvg		      "4"
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      AxisGrid		      on
      Memory		      off
      FrameNumber	      on
      AxisLegend	      off
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      OpenScopeAtSimStart     on
      OpenScopeImmediately    off
      FigPos		      "get(0,'defaultfigureposition')"
      AxisProperties	      off
      XUnits		      "Hertz"
      XRange		      "[0...Fs/2]"
      InheritXIncr	      on
      XIncr		      "1.0"
      XLabel		      "Samples"
      YUnits		      "dB"
      YMin		      "18.828197519954"
      YMax		      "96.4746727176919"
      YLabel		      "Magnitude-squared, dB"
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      wintypeSpecScope	      "Hann"
      RsSpecScope	      "50"
      betaSpecScope	      "5"
      winsampSpecScope	      "Periodic"
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      BlockType		      Scope
      Name		      "In Phase Out"
      Ports		      [5]
      Position		      [2205, 323, 2260, 447]
      NamePlacement	      "alternate"
      Floating		      off
      Location		      [6, 57, 1276, 982]
      Open		      off
      NumInputPorts	      "5"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
	axes4			"%<SignalLabel>"
	axes5			"%<SignalLabel>"
      }
      YMin		      "0~-50000~0~0~-1"
      YMax		      "1~300000~1~1~1"
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      SampleTime	      "0"
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      Open		      off
      NumInputPorts	      "5"
      ZoomMode		      "xonly"
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	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
	axes4			"%<SignalLabel>"
	axes5			"%<SignalLabel>"
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      YMin		      "-5~-5~-5~-5~-5"
      YMax		      "5~5~5~5~5"
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      Name		      "Rounding"
      Ports		      [5, 5]
      Position		      [1295, 336, 1435, 534]
      ForegroundColor	      "green"
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      MaskType		      "SubSystem AlteraBlockSet"
      MaskSelfModifiable      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"Rounding"
	Location		[2, 84, 1270, 971]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
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	  IconDisplay		  "Port number"
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	  Name			  "In_data[34:0]"
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	  ForegroundColor	  "blue"
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	  Name			  "In_eop"
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	  ForegroundColor	  "blue"
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	Block {
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	  Name			  "In_sop"
	  Position		  [45, 598, 75, 612]
	  ForegroundColor	  "blue"
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	  IconDisplay		  "Port number"
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	Block {
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	  Name			  "In_valid"
	  Position		  [45, 523, 75, 537]
	  ForegroundColor	  "blue"
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	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Round"
	  Ports			  [1, 1]
	  Position		  [390, 410, 455, 430]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Round"
	  SourceType		  "HDLEntity AlteraBlockSet"
	  BusType		  "Signed Integer"
	  bwl			  "33"
	  bwr			  "0"
	  altrlsb		  "17"
	  RoundTypeAltr		  "Truncate"
	  PipelineAltr		  off
	  SIGNALCOMPILER_PARAMS	  "HDLInputPortsMappingAltera;xin.33.0.s;HDLOu"
"tputPortsMappingAltera;yout.16.0.s;HDLParameterMappingAltera;widthin.33.natur"
"al,widthout.16.natural,bround.0.natural,lpm_representation.\"SIGNED\".natural"
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	  SourceType		  "HDLEntity AlteraBlockSet"
	  BusType		  "Signed Integer"
	  bwl			  "35"
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	  altrlsb		  "2"
	  SatTypeAltr		  "Saturate"
	  UpperValue		  "4294967295"
	  LowerValue		  "-4294967296"
	  PipelineAltr		  off
	  UpperValueFmt		  "4294967295"
	  LowerValueFmt		  "-4294967296"
	  SIGNALCOMPILER_PARAMS	  "HDLInputPortsMappingAltera;xin.35.0.s;HDLOu"
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	  BlockType		  Reference
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	  Position		  [105, 412, 170, 428]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "35"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "in_data"
	  ppat			  "d:\\dspbuilder\\Altlib\\DSPBuilder_allblock"
"s_alteradspbuilder"
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	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
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	Block {
	  BlockType		  Reference
	  Name			  "in_eop"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [95, 672, 160, 688]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
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	  LocPin		  "any"
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	  modulename		  "in_eop"
	  ppat			  "d:\\dspbuilder\\Altlib\\DSPBuilder_allblock"
"s_alteradspbuilder"
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	  BlockType		  Reference
	  Name			  "in_ready"
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	  SourceBlock		  "allblocks_alteradspbuilder/Output"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Output Port"
	  bwl			  "8"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "Output"
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	  SIGNALCOMPILER_PARAMS	  "sgn;Single Bit;nodetype;Output Port;bwl;1;b"
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	  BlockType		  Reference
	  Name			  "in_sop"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [100, 597, 165, 613]
	  ForegroundColor	  "blue"
	  SourceBlock		  "allblocks_alteradspbuilder/Input"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Single Bit"
	  nodetype		  "Input Port"

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