stimulus.v

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/***********************************************************************
 
  File:   stimulus.v
  Rev:    3.0.0

  This is a functional simulation model for a stimulus generator.
  This is not synthesizable.  This file is only for simulation.

  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.

***********************************************************************/


module stimulus (
                AD,
                CBE,
                PAR,
                PAR64,
                FRAME_N,
                REQ64_N,
                TRDY_N,
                IRDY_N,
                STOP_N,
                DEVSEL_N,
                ACK64_N,
                IDSEL,
                INTR_A,
                PERR_N,
                SERR_N,
                RST_N,
                CLK,
                SINGLE,
                PARK,
                PING_DONE,
                PING_REQUEST32,
                PING_REQUEST64
                );


  inout  [63:0] AD;
  inout   [7:0] CBE;
  inout         PAR;
  inout         PAR64;
  inout         FRAME_N;
  inout         REQ64_N;
  inout         TRDY_N;
  inout         IRDY_N;
  inout         STOP_N;
  inout         DEVSEL_N;
  inout         ACK64_N;
  output        IDSEL;
  input         INTR_A;
  input         PERR_N;
  input         SERR_N;
  output        RST_N;
  output        CLK;
  output        SINGLE;
  output        PARK;
  input         PING_DONE;
  output        PING_REQUEST32;
  output        PING_REQUEST64;


  // Define Timing Parameters

  parameter TCLKH = 7;
  parameter TCLKL = 8;
  parameter TDEL =  5;


  // Define Internal Registers

  reg           pciclk;
  reg           pciclk_en;
  reg  [8*12:1] operation;
  reg     [3:0] status_code;

  reg    [63:0] reg_ad;
  reg           adh_oe;
  reg           adl_oe;
  reg     [7:0] reg_cbe;
  reg           cbeh_oe;
  reg           cbel_oe;
  reg           reg_par;
  reg           par_oe;
  reg           reg_par64;
  reg           par64_oe;
  reg           reg_frame_n;
  reg           frame_oe;
  reg           reg_req64_n;
  reg           req64_oe;
  reg           reg_trdy_n;
  reg           trdy_oe;
  reg           reg_irdy_n;
  reg           irdy_oe;
  reg           reg_stop_n;
  reg           stop_oe;
  reg           reg_devsel_n;
  reg           devsel_oe;
  reg           reg_ack64_n;
  reg           ack64_oe;

  reg           reg_idsel;
  reg           reg_rst_n;
  reg           reg_single;
  reg           reg_park;
  reg           reg_req32;
  reg           reg_req64;


  // Define port hookup

  assign #TDEL AD = adh_oe ? {reg_ad[63:32],32'bz} : 64'bz;
  assign #TDEL AD = adl_oe ? {32'bz,reg_ad[31: 0]} : 64'bz;
  assign #TDEL CBE = cbeh_oe ? {reg_cbe[7:4],4'bz} : 8'bz;
  assign #TDEL CBE = cbel_oe ? {4'bz,reg_cbe[3:0]} : 8'bz;
  assign #TDEL PAR = par_oe ? reg_par : 1'bz;
  assign #TDEL PAR64 = par64_oe ? reg_par64 : 1'bz;

  assign #TDEL FRAME_N = frame_oe ? reg_frame_n : 1'bz;
  assign #TDEL REQ64_N = req64_oe ? reg_req64_n : 1'bz;
  assign #TDEL TRDY_N = trdy_oe ? reg_trdy_n : 1'bz;
  assign #TDEL IRDY_N = irdy_oe ? reg_irdy_n : 1'bz;
  assign #TDEL STOP_N = stop_oe ? reg_stop_n : 1'bz;
  assign #TDEL DEVSEL_N = devsel_oe ? reg_devsel_n : 1'bz;
  assign #TDEL ACK64_N = ack64_oe ? reg_ack64_n : 1'bz;
  assign #TDEL IDSEL = reg_idsel;
  assign #TDEL RST_N = reg_rst_n;
  assign #TDEL SINGLE = reg_single;
  assign #TDEL PARK = reg_park;
  assign #TDEL PING_REQUEST32 = reg_req32;
  assign #TDEL PING_REQUEST64 = reg_req64;


  // Clock generation

  always
  begin
    pciclk <= 0;
    #TCLKL;
    pciclk <= pciclk_en;
    #TCLKH;
  end

  assign CLK = pciclk;


  // PCI Parity Generation

  always @(posedge pciclk)
  begin
    // Always computed, selectively enabled
    reg_par <= (^ {AD[31:0], CBE[3:0]} );
    reg_par64 <= (^ {AD[63:32], CBE[7:4]} );
  end

  wire driveh;
  wire drivel;

  assign #TDEL driveh = adh_oe;
  assign #TDEL drivel = adl_oe;

  always @(posedge pciclk)
  begin
    par_oe <= drivel;
    par64_oe <= driveh;
  end


  // Task for reading from the PCI64's configuration space
  // Looks like 32-bit configurator plugged into 64-bit system
  // or the PCI64 plugged into a 32-bit slot

  task READ_CONFIG;
    input [31:0] address;
  begin
    $display(" ");
    $display("Reading Ping Config Reg...");
    operation <= "READ_CFG_32 ";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'bz,address};
      reg_cbe <= {4'bz,4'b1010};
      reg_idsel <= 1;
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_irdy_n <= 0;
      reg_cbe <= {4'bz,4'b0000};
      reg_idsel <= 0;
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 1;
      XFER_STATUS(0, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for writing to the PCI64's configuration space
  // Looks like 32-bit configurator plugged into 64-bit system
  // or the PCI64 plugged into a 32-bit slot

  task WRITE_CONFIG;
    input [31:0] address;
    input [63:0] data;
  begin
    $display(" ");
    $display("Writing Ping Config Reg...");
    operation <= "WRITE_CFG_32";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'bz,address};
      reg_cbe <= {4'bz,4'b1011};
      reg_idsel <= 1;
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_irdy_n <= 0;
      reg_ad <= {32'bz,data[31:0]};
      reg_cbe <= {4'bz,4'b0000};
      reg_idsel <= 0;
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
      XFER_STATUS(1, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for reading from the PCI64
  // Looks like 32-bit agent plugged into 64-bit system
  // or the PCI64 plugged into a 32-bit slot

  task READ32;
    input  [3:0] command;
    input [31:0] address;
  begin
    $display(" ");
    $display("Reading Ping...");
    operation <= "READ_PNG_32 ";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'bz,address};
      reg_cbe <= {4'bz,command};
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_irdy_n <= 0;
      reg_cbe <= {4'bz,4'b0000};
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 1;
      XFER_STATUS(0, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for reading from the PCI64
  // Looks like 64-bit agent plugged into 64-bit system
  // attempting a 64-bit transfer

  task READ64;
    input  [3:0] command;
    input [31:0] address;
  begin
    $display(" ");
    $display("Reading Ping...");
    operation <= "READ_PNG_64 ";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_req64_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'b0,address};
      reg_cbe <= {4'b0,command};
      frame_oe <= 1;
      req64_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      adh_oe <= 1;
      cbel_oe <= 1;
      cbeh_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_req64_n <= 1;
      reg_irdy_n <= 0;
      reg_cbe <= 8'b00000000;
      frame_oe <= 1;
      req64_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 0;
      adh_oe <= 0;
      cbel_oe <= 1;
      cbeh_oe <= 1;
      XFER_STATUS(0, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      req64_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      adh_oe <= 0;
      cbel_oe <= 0;
      cbeh_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      req64_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for writing to the PCI64
  // Looks like 32-bit agent plugged into 64-bit system
  // or the PCI64 plugged into a 32-bit slot

  task WRITE32;
    input  [3:0] command;
    input [31:0] address;
    input [63:0] data;
  begin
    $display(" ");
    $display("Writing Ping...");
    operation <= "WRITE_PNG_32";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'bz,address};
      reg_cbe <= {4'bz,command};
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_irdy_n <= 0;
      reg_ad <= {32'bz,data[31:0]};
      reg_cbe <= {4'bz,4'b0000};
      frame_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      cbel_oe <= 1;
      XFER_STATUS(1, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      cbel_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for writing to the PCI64
  // Looks like 64-bit agent plugged into 64-bit system
  // doing a 64-bit transfer

  task WRITE64;
    input  [3:0] command;
    input [31:0] address;
    input [63:0] data;
  begin
    $display(" ");
    $display("Writing Ping...");
    operation <= "WRITE_PNG_64";
    @(posedge pciclk);
      reg_frame_n <= 0;
      reg_req64_n <= 0;
      reg_irdy_n <= 1;
      reg_ad <= {32'b0,address};
      reg_cbe <= {4'b0,command};
      frame_oe <= 1;
      req64_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      adh_oe <= 1;
      cbel_oe <= 1;
      cbeh_oe <= 1;
    @(posedge pciclk);
      reg_frame_n <= 1;
      reg_req64_n <= 1;
      reg_irdy_n <= 0;
      reg_ad <= data;
      reg_cbe <= 8'b00000000;
      frame_oe <= 1;
      req64_oe <= 1;
      irdy_oe <= 1;
      adl_oe <= 1;
      adh_oe <= 1;
      cbel_oe <= 1;
      cbeh_oe <= 1;
      XFER_STATUS(1, status_code);
      reg_irdy_n <= 1;
      frame_oe <= 0;
      req64_oe <= 0;
      irdy_oe <= 1;
      adl_oe <= 0;
      adh_oe <= 0;
      cbel_oe <= 0;
      cbeh_oe <= 0;
    @(posedge pciclk);
      frame_oe <= 0;
      req64_oe <= 0;
      irdy_oe <= 0;
    @(posedge pciclk);
    INTERCYCLE_GAP;
  end
  endtask


  // Task for monitoring the actual data transfer

  task XFER_STATUS;
    input write_read;
    output [3:0] return_stat;
    integer devsel_cnt;
    integer trdy_cnt;
  begin
    devsel_cnt = 0;
    trdy_cnt = 0;
    while(DEVSEL_N && (devsel_cnt < 10))
    begin
      @(posedge pciclk);
      devsel_cnt = devsel_cnt + 1; // increment count
    end
    while(TRDY_N  && STOP_N && ((trdy_cnt < 16) && (devsel_cnt < 10)))
    begin
      // Turn off extension if not 64-bit
      if (write_read == 1) adh_oe = !ACK64_N;
      cbeh_oe = !ACK64_N;
      trdy_cnt = trdy_cnt + 1;
      @(posedge pciclk);
    end
    if (devsel_cnt < 10)
      begin
        if (trdy_cnt <= 16)
          begin
            if (TRDY_N == 0 && STOP_N == 1)
            begin
              if (write_read)
                $display("  STM-->PNG: Normal Termination, Data Transferred");
              else
                $display("  STM<--PNG: Normal Termination, Data Transferred");
              return_stat = 1;
            end
            else if(TRDY_N == 0 && STOP_N == 0)
            begin
              if (write_read)
                $display("  STM-->PNG: Disconnect, Data Transferred");
              else
                $display("  STM<--PNG: Disconnect, Data Transferred");
              return_stat = 2;
            end
            else if (TRDY_N==1 && STOP_N == 0 && DEVSEL_N == 0)
            begin
              if (write_read)
                $display("  STM-->PNG: Retry, No Data Transferred");
              else
                $display("  STM<--PNG: Retry, No Data Transferred");
              return_stat = 3;
            end
            else if (TRDY_N==1 && STOP_N == 0 && DEVSEL_N == 1)
            begin
              if (write_read)
                $display("  STM-->PNG: Target Abort, No Data Transferred");
              else
                $display("  STM<--PNG: Target Abort, No Data Transferred");
              return_stat = 4;
            end
            else if (TRDY_N==1 && STOP_N == 1)
            begin
              $display("  ERROR: Check Transfer Procedure");
              return_stat = 5;
            end
          end
        else
        begin
          $display("  ERROR: No Target Response");
          return_stat = 6;
        end
      end
    else
    begin
      $display("  ERROR: Master Abort");
      return_stat = 7;
    end
  end
  endtask


  // Task for waiting

  task INTERCYCLE_GAP;
  begin
    @(posedge pciclk);
    @(posedge pciclk);
    @(posedge pciclk);
    @(posedge pciclk);
  end
  endtask


  // Task for starting 32-bit transfer

  task MOVE32;
  begin
    @(posedge pciclk);
    reg_req32 <= 1'b1;
    @(posedge pciclk);
    reg_req32 <= 1'b0;
    @(posedge pciclk);
    wait (PING_DONE);
    @(posedge pciclk);
  end
  endtask


  // Task for starting 64-bit transfer

  task MOVE64;
  begin
    @(posedge pciclk);
    reg_req64 <= 1'b1;
    @(posedge pciclk);
    reg_req64 <= 1'b0;
    @(posedge pciclk);
    wait (PING_DONE);
    @(posedge pciclk);
  end
  endtask


  // Tasks for bus parking

  task ARB_PARK;
  begin
    @(posedge pciclk);
    reg_park <= 1'b1;
    @(posedge pciclk);
  end
  endtask

  task ARB_FREE;
  begin    
    @(posedge pciclk); 
    reg_park <= 1'b0; 
    @(posedge pciclk); 
  end