stimulus.v

来自「xilinx官方PCIcore 有详细说明文档」· Verilog 代码 · 共 1,194 行 · 第 1/2 页

  endtask 


  // Tasks for single cycle grants

  task ARB_SINGLE;
  begin    
    @(posedge pciclk); 
    reg_single <= 1'b1; 
    @(posedge pciclk); 
  end 
  endtask 

  task ARB_FOLLOW; 
  begin     
    @(posedge pciclk);  
    reg_single <= 1'b0;  
    @(posedge pciclk);  
  end    
  endtask  


  // Begin the actual simulation sequence

  initial
  begin
    // start by setting up all signals
    operation <= "SYSTEM RESET";
    pciclk_en <= 1;
    reg_ad <= 64'h0;
    adh_oe <= 0;
    adl_oe <= 0;
    reg_cbe <= 8'h0;
    cbeh_oe <= 0;
    cbel_oe <= 0;
    reg_frame_n <= 1;
    frame_oe <= 0;
    reg_req64_n <= 1;
    req64_oe <= 0;
    reg_trdy_n <= 1;
    trdy_oe <= 0;
    reg_irdy_n <= 1;
    irdy_oe <= 0;
    reg_stop_n <= 1;
    stop_oe <= 0;
    reg_devsel_n <= 1;
    devsel_oe <= 0;
    reg_ack64_n <= 1;
    ack64_oe <= 0;
    reg_idsel <= 0;
    reg_rst_n <= 0;
    reg_single <= 0;
    reg_park <= 0;
    reg_req32 <= 0;
    reg_req64 <= 0;

    // release system reset
    INTERCYCLE_GAP;
    reg_rst_n <= 1;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("System Reset Complete...");
    $display(" ");


    // read device and vendor id
    READ_CONFIG(32'h00000000);

    // write latency timer
    WRITE_CONFIG(32'h0000000c, 64'h000000000000ff00);
    READ_CONFIG(32'h0000000c);


    // setup io base address register
    WRITE_CONFIG(32'h00000010, 64'h0000000010000000);
    READ_CONFIG(32'h00000010);

    // setup mem32 base address register
    WRITE_CONFIG(32'h00000014, 64'h0000000020000000);
    READ_CONFIG(32'h00000014);

    // setup mem64 base address register
    WRITE_CONFIG(32'h00000018, 64'h0000000030000000);
    READ_CONFIG(32'h00000018);

    // setup command register to enable mastering
    WRITE_CONFIG(32'h00000004, 64'h00000000ff000147); 
    READ_CONFIG(32'h00000004);


    // read io space
    READ32(4'b0010, 32'h10000000);
 
    // read io space
    READ64(4'b0010, 32'h10000000);
 
 
    // write io space
    WRITE32(4'b0011, 32'h10000000, 64'h0000000020202020);
    READ32(4'b0010, 32'h10000000);
 
    // write io space
    WRITE64(4'b0011, 32'h10000000, 64'h0000000030303030);
    READ64(4'b0010, 32'h10000000);
 

    // read mem32 space
    READ32(4'b0110, 32'h20000000);
 
    // read mem32 space
    READ64(4'b0110, 32'h20000000);


    // write mem32 space
    WRITE32(4'b0111, 32'h20000000, 64'h0000000016161616);
    READ32(4'b0110, 32'h20000000);

    // write mem32 space
    WRITE64(4'b0111, 32'h20000000, 64'h0000000008080808);
    READ64(4'b0110, 32'h20000000);


    // read mem64 space
    READ32(4'b0110, 32'h30000000);
 
    // read mem64 space
    READ64(4'b0110, 32'h30000000);


    // write mem64 space
    WRITE32(4'b0111, 32'h30000000, 64'ha5a5a5a5a5a5a5a5);
    READ32(4'b0110, 32'h30000000);

    // write mem64 space
    WRITE64(4'b0111, 32'h30000000, 64'h5a5a5a5a5a5a5a5a);
    READ64(4'b0110, 32'h30000000);


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Performing 32-bit initiator transfers...");
    $display(" ");


    // set up one-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000004);
    MOVE32;

    // set up two-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000008);
    MOVE32;

    // set up three-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000010);
    MOVE32;

    // set up four-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000004000001c);
    MOVE32;

    // set up one-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000004);
    MOVE32;

    // set up two-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000008);
    MOVE32;

    // set up three-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000010);
    MOVE32;

    // set up four-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000004000001c);
    MOVE32;


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Performing 64-bit initiator transfers...");
    $display(" ");


    // set up one-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000004);
    MOVE64;

    // set up two-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000008);
    MOVE64;

    // set up three-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000010);
    MOVE64;

    // set up four-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000001c);
    MOVE64;

    // set up one-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000004);
    MOVE64;

    // set up two-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000008);
    MOVE64;

    // set up three-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000010);
    MOVE64;

    // set up four-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000001c);
    MOVE64;


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Performing 32-bit initiator transfers from park...");
    $display(" ");


    // set up one-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000044);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up two-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000048);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up three-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000050);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up four-dataphase 32-bit initiator  read to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000004000005c);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up one-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000044);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up two-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000048);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up three-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000040000050);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up four-dataphase 32-bit initiator write to 32-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000004000005c);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE32;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Performing 64-bit initiator transfers from park...");
    $display(" ");


    // set up one-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000044);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up two-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000048);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up three-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000050);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up four-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000005c);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up one-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000061);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000044);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up two-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000048);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up three-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000050);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;

    // set up four-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000005c);
    ARB_PARK;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    MOVE64;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    ARB_FREE;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Turning off 64-bitness...");
    $display(" ");


    // disable slot64
    WRITE_CONFIG(32'h00000040, 64'h00000000ffffffff);
    READ_CONFIG(32'h00000040);


    // read mem32 space
    READ32(4'b0110, 32'h20000000);
 
    // read mem32 space
    READ64(4'b0110, 32'h20000000);
 
 
    // write mem32 space
    WRITE32(4'b0111, 32'h20000000, 64'h0000000016161616);
    READ32(4'b0110, 32'h20000000);
 
    // write mem32 space
    WRITE64(4'b0111, 32'h20000000, 64'h0000000008080808);
    READ64(4'b0110, 32'h20000000);
 
 
    // read mem64 space
    READ32(4'b0110, 32'h30000000);
 
    // read mem64 space
    READ64(4'b0110, 32'h30000000);
 
 
    // write mem64 space 
    WRITE32(4'b0111, 32'h30000000, 64'ha5a5a5a5a5a5a5a5);
    READ32(4'b0110, 32'h30000000);
 
    // write mem64 space
    WRITE64(4'b0111, 32'h30000000, 64'h5a5a5a5a5a5a5a5a);
    READ64(4'b0110, 32'h30000000);


    // set up two-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000008);
    MOVE64;

    // set up three-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000010);
    MOVE64;

    // set up four-dataphase 64-bit initiator  read to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000000000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000001c);
    MOVE64;

    // set up two-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000062);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000008);
    MOVE64;

    // set up three-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000063);
    WRITE32(4'b0111, 32'h20000000, 64'h0000000050000010);
    MOVE64;

    // set up four-dataphase 64-bit initiator write to 64-bit target
    WRITE32(4'b0011, 32'h10000000, 64'h0000000080000064);
    WRITE32(4'b0111, 32'h20000000, 64'h000000005000001c);
    MOVE64;


    $display(" ");
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    INTERCYCLE_GAP;
    $display(" ");
    $display("Simulation complete...");
    $display(" ");

    // disable pciclk
    pciclk_en <= 0;

    // stop simulation
    $finish;
  end


endmodule