mux16x1_2_4x1.tf

VHDL examples for 16x16 times, if need detail pls let me know

`timescale 1ns/1ns
`define period 60

module functional (selA, dataA, selB, dataB, selC, dataC, outA, outB, outC);
input [3:0] selA, dataB, dataC;
input [15:0] dataA;
input [1:0] selB, selC;
output outA, outB, outC;
reg outA, outB, outC;

always @(selA or dataA) begin
	case (selA)
		4'h0 : outA <= dataA[0];
	    4'h1 : outA <= dataA[1];
	   	4'h2 : outA <= dataA[2];
	   	4'h3 : outA <= dataA[3];
	   	4'h4 : outA <= dataA[4];
	   	4'h5 : outA <= dataA[5];
	   	4'h6 : outA <= dataA[6];
	   	4'h7 : outA <= dataA[7];
	   	4'h8 : outA <= dataA[8];
	   	4'h9 : outA <= dataA[9];
	   	4'hA : outA <= dataA[10];
	   	4'hB : outA <= dataA[11];
	   	4'hC : outA <= dataA[12];
	   	4'hD : outA <= dataA[13];
	   	4'hE : outA <= dataA[14];
	   	4'hF : outA <= dataA[15];
	endcase

end

always @(selB or dataB) begin
	case (selB)
		2'h0 : outB <= dataB[0];
		2'h1 : outB <= dataB[1];
		2'h2 : outB <= dataB[2];
		2'h3 : outB <= dataB[3];

	endcase

end

always @(selC or dataC) begin
	case (selC)
		2'h0 : outC <= dataC[0];
		2'h1 : outC <= dataC[1];
		2'h2 : outC <= dataC[2];
		2'h3 : outC <= dataC[3];
		
	endcase

end

endmodule



module t;

reg [15:0] dataA;
reg [3:0] dataB;
reg [3:0] dataC;
wire outA, outB, outC;
reg [3:0] selA;
reg [1:0] selB;
reg [1:0] selC;
wire countA, countB, countC;
integer cycles;

    mux16x1_2_4x1 m ( .dataA(dataA), .dataB(dataB), .dataC(dataC), .outA(outA),
    				.outB(outB), .outC(outC), .selA(selA), .selB(selB), .selC(selC) );
	functional m2 ( .dataA(dataA), .dataB(dataB), .dataC(dataC), .selA(selA), .selB(selB), 
					.selC(selC), .outA(countA), .outB(countB), .outC(countC)); 
    // Enter fixture code here
initial begin
   dataA = 16'h0;
   forever begin
      #(`period*3);
      dataA = $random;
   end
end  

initial begin
   dataB = 4'h0;
   forever begin
      #(`period*3);
      dataB = $random;
   end
end

initial begin
   dataC = 4'h0;
   forever begin
      #(`period*3);
      dataC = $random;
   end
end

initial begin
   selA = 4'h0;
   forever begin
      #(`period*3);
      selA = $random;
   end
end

initial begin
   selB = 2'h0;
   forever begin
      #(`period*3);
      selB = $random;
   end
end

initial begin
   selC = 2'h0;
   forever begin
      #(`period*2);
      selC = $random;
   end
end

initial begin
   #(`period);
   cycles = 0;
   forever begin
      #(`period*4);
	if (countA != outA) begin
	   $display ("Error: At time %t, outA = %h should be %h",$time, outA, countA);
	   $stop;
       end
	else begin
           cycles = cycles + 1;
           if ((cycles % 100) == 0) 
              $display ("Completed %d cycles", cycles);
         end
    end
end

initial begin
   #(`period);
   cycles = 0;
   forever begin
      #(`period*4);
	if (countB != outB) begin
	   $display ("Error: At time %t, outB = %h should be %h",$time, outB, countB);
	   $stop;
       end
	else begin
           cycles = cycles + 1;
           if ((cycles % 100) == 0) 
              $display ("Completed %d cycles", cycles);
         end
    end
end

initial begin
   #(`period);
   cycles = 0;
   forever begin
      #(`period*4);
	if (countC != outC) begin
	   $display ("Error: At time %t, outC = %h should be %h",$time, outC, countC);
	   $stop;
       end
	else begin
           cycles = cycles + 1;
           if ((cycles % 100) == 0) 
              $display ("Completed %d cycles", cycles);
         end
    end
end

endmodule // t