readme.txt

来自「VHDL examples for 16x16 times, if need d」· 文本 代码 · 共 13 行

This zip file contains the schematics and the symbols so that the user can directly use it in his/her design.

The mux16x1_4x1.sch is the schematic that implements the muxes in 5 logic cells.
The mux16x1_4x1.sym is the symbol that the user can directly add into his/her design.

The mux16x1_2_4x1.* are the files that allows the user to test the funcionality of the mux16x1_4x1 design. 
It includes:
	-the verilog (.v and .vq), 
	-the test fixture (.tf), 
	-the waveform editor files (.wdl, .wav, .wet), 
	-the standard delay file (.sdf), 
	-Hierarchy Navigator file (.tre)