mux16x1_2_4x1.v

VHDL examples for 16x16 times, if need detail pls let me know

/* Verilog Model Created from SCS Schematic mux16x1_2_4x1.sch 
   Oct 04, 1999 16:50 */

/* Automatically generated by hvveri version 8.1  */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 

module mux16x1_2_4x1( dataA, dataB, dataC, outA, outB, outC, selA, selB, selC );
 input [15:0] dataA;
 input [3:0] dataB;
 input [3:0] dataC;
output outA, outB, outC;
 input [3:0] selA;
 input [1:0] selB;
 input [1:0] selC;
parameter syn_macro = 1;

mux16x1_4x1 I1 ( .IN0(dataA[0]), .IN0_4A(dataB[0]), .IN0_4B(dataC[0]),
              .IN1(dataA[1]), .IN10(dataA[10]), .IN11(dataA[11]),
              .IN12(dataA[12]), .IN13(dataA[13]), .IN14(dataA[14]),
              .IN15(dataA[15]), .IN1_4A(dataB[1]), .IN1_4B(dataC[1]),
              .IN2(dataA[2]), .IN2_4A(dataB[2]), .IN2_4B(dataC[2]),
              .IN3(dataA[3]), .IN3_4A(dataB[3]), .IN3_4B(dataC[3]),
              .IN4(dataA[4]), .IN5(dataA[5]), .IN6(dataA[6]), .IN7(dataA[7]),
              .IN8(dataA[8]), .IN9(dataA[9]), .Q_16(outA), .Q_4A(outB),
              .Q_4B(outC), .S0_16(selA[0]), .S0_4A(selB[0]), .S0_4B(selC[0]),
              .S1_16(selA[1]), .S1_4A(selB[1]), .S1_4B(selC[1]),
              .S2_16(selA[2]), .S3_16(selA[3]) );

endmodule // mux16x1_2_4x1


`ifdef mux16x1_4x1
`else
`define mux16x1_4x1
module mux16x1_4x1( IN0, IN0_4A, IN0_4B, IN1, IN10, IN11, IN12, IN13, IN14, IN15,
                    IN1_4A, IN1_4B, IN2, IN2_4A, IN2_4B, IN3, IN3_4A, IN3_4B,
                    IN4, IN5, IN6, IN7, IN8, IN9, Q_16, Q_4A, Q_4B, S0_16,
                    S0_4A, S0_4B, S1_16, S1_4A, S1_4B, S2_16, S3_16 );
input IN0, IN0_4A, IN0_4B, IN1, IN10, IN11, IN12, IN13, IN14, IN15, IN1_4A,
IN1_4B, IN2, IN2_4A, IN2_4B, IN3, IN3_4A, IN3_4B, IN4, IN5, IN6, IN7,
IN8, IN9;
output Q_16, Q_4A, Q_4B;
input S0_16, S0_4A, S0_4B, S1_16, S1_4A, S1_4B, S2_16, S3_16;
parameter syn_macro = 1;
parameter ql_pack = 1;

wire M_Q1;
wire r3;
wire M_Q0;
wire M_Q2;
wire r4;
wire M_Q3;
wire r1;
supply1 VCC;
wire MB_Q3;
wire MB_Q1;
wire Q3;
wire Q2;
wire Q1;
wire Q0;
wire MB_Q2;
wire MB_Q0;
wire r2;
supply0 GND;

logic2 I13 ( .A1(IN0_4B), .A2(GND), .A3(VCC), .A4(S1_4B), .A5(VCC), .A6(S0_4B),
          .AZ(MB_Q3), .B1(IN12), .B2(GND), .C1(IN13), .C2(GND), .D1(IN14),
          .D2(GND), .E1(IN15), .E2(GND), .F1(IN1_4B), .F2(GND), .F3(VCC),
          .F4(S1_4B), .F5(S0_4B), .F6(GND), .FZ(MB_Q2), .MP(GND), .MS(S0_16),
          .NP(GND), .NS(S0_16), .OP(GND), .OS(S1_16), .OZ(Q0), .QC(GND),
          .QR(GND), .QS(GND) );
logic2 I14 ( .A1(IN2_4B), .A2(GND), .A3(VCC), .A4(GND), .A5(S1_4B), .A6(S0_4B),
          .AZ(MB_Q1), .B1(Q3), .B2(GND), .C1(Q2), .C2(GND), .D1(Q1), .D2(GND),
          .E1(Q0), .E2(GND), .F1(IN3_4B), .F2(GND), .F3(S1_4B), .F4(GND),
          .F5(S0_4B), .F6(GND), .FZ(MB_Q0), .MP(GND), .MS(S2_16), .NP(GND),
          .NS(S2_16), .OP(GND), .OS(S3_16), .OZ(Q_16), .QC(VCC), .QR(r2),
          .QS(VCC), .QZ(Q_4B) );
logic2 I15 ( .A1(r3), .A2(M_Q2), .A3(VCC), .A4(M_Q1), .A5(VCC), .A6(M_Q0), .AZ(r1),
          .B1(IN8), .B2(GND), .C1(IN9), .C2(GND), .D1(IN10), .D2(GND), .E1(IN11),
          .E2(GND), .F1(r4), .F2(MB_Q2), .F3(VCC), .F4(MB_Q1), .F5(VCC),
          .F6(MB_Q0), .FZ(r2), .MP(GND), .MS(S0_16), .NP(GND), .NS(S0_16),
          .OP(GND), .OS(S1_16), .OZ(Q1), .QC(VCC), .QR(r1), .QS(VCC), .QZ(Q_4A) );
logic2 I16 ( .A1(IN2_4A), .A2(GND), .A3(VCC), .A4(GND), .A5(S1_4A), .A6(S0_4A),
          .AZ(M_Q1), .B1(IN4), .B2(GND), .C1(IN5), .C2(GND), .D1(IN6), .D2(GND),
          .E1(IN7), .E2(GND), .F1(IN3_4A), .F2(GND), .F3(S1_4A), .F4(GND),
          .F5(S0_4A), .F6(GND), .FZ(M_Q0), .MP(GND), .MS(S0_16), .NP(GND),
          .NS(S0_16), .OP(GND), .OS(S1_16), .OZ(Q2), .QC(VCC), .QR(M_Q3),
          .QS(VCC), .QZ(r3) );
logic2 I17 ( .A1(IN0_4A), .A2(GND), .A3(VCC), .A4(S1_4A), .A5(VCC), .A6(S0_4A),
          .AZ(M_Q3), .B1(IN0), .B2(GND), .C1(IN1), .C2(GND), .D1(IN2), .D2(GND),
          .E1(IN3), .E2(GND), .F1(IN1_4A), .F2(GND), .F3(VCC), .F4(S1_4A),
          .F5(S0_4A), .F6(GND), .FZ(M_Q2), .MP(GND), .MS(S0_16), .NP(GND),
          .NS(S0_16), .OP(GND), .OS(S1_16), .OZ(Q3), .QC(VCC), .QR(MB_Q3),
          .QS(VCC), .QZ(r4) );

endmodule // mux16x1_4x1

`endif

`ifdef logic2
`else
`define logic2
module logic2( A1, A2, A3, A4, A5, A6, AZ, B1, B2, C1, C2, D1, D2, E1, E2, F1,
               F2, F3, F4, F5, F6, FZ, MP, MS, NP, NS, NZ, OP, OS, OZ, QC, QR,
               QS, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;

lcell2 I_2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ), .B1(B1),
          .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1), .E2(E2), .F1(F1),
          .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6), .FZ(FZ), .MP(MP), .MS(MS),
          .NP(NP), .NS(NS), .NZ(NZ), .OP(OP), .OS(OS), .OZ(OZ), .QC(QC), .QR(QR),
          .QS(QS), .QZ(QZ) );

endmodule // logic2

`endif

`ifdef lcell2
`else
`define lcell2
module lcell2( A1, A2, A3, A4, A5, A6, AZ, B1, B2, C1, C2, D1, D2, E1, E2, F1,
               F2, F3, F4, F5, F6, FZ, MP, MS, NP, NS, NZ, OP, OS, OZ, QC, QR,
               QS, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_frag = 1;
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z; 
 wire MZ; 
 reg QZ; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS;  
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2):(B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS;  
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2):(D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS;  
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ;  
`ifdef synthesis 
 always @ (posedge QC or posedge QR or posedge QS)  
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else #1 QZ = OZ; 
`else 
  always @ (posedge QC) 
      if (~QR && ~QS) 
         QZ = #1 OZ; 
  always @ (QR or QS) 
      if (QR) 
         QZ = #1 1'b0; 
      else if (QS) 
         QZ = #1 1'b1; 
 `endif 

endmodule // lcell2

`endif