fre_test.map.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[13\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[13\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[14\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[14\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[15\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[15\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[16\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[16\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[17\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[17\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[18\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[18\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[19\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[19\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[20\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[20\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[21\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[21\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[22\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[22\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[23\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[23\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[24\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[24\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[25\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[25\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[26\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[26\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[27\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[27\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[28\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[28\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[29\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[29\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[30\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[30\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[31\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[31\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tf.vhd 2 1 " "Warning: Using design file tf.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tf-behav " "Info: Found design unit 1: tf-behav" {  } { { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tf " "Info: Found entity 1: tf" {  } { { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tf tf:inst2 " "Info: Elaborating entity \"tf\" for hierarchy \"tf:inst2\"" {  } { { "fre_test.bdf" "inst2" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 160 280 400 256 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "152 " "Info: Implemented 152 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "136 " "Info: Implemented 136 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:56:20 2008 " "Info: Processing ended: Fri May 09 10:56:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}