fre_test.map.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 09 10:56:16 2008 " "Info: Processing started: Fri May 09 10:56:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fre_test -c fre_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fre_test -c fre_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fre_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fre_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fre_test " "Info: Found entity 1: fre_test" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux模块/mux64_8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux模块/mux64_8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux64_8-behav " "Info: Found design unit 1: mux64_8-behav" {  } { { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux64_8 " "Info: Found entity 1: mux64_8" {  } { { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fre_test " "Info: Elaborating entity \"fre_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux64_8 mux64_8:inst3 " "Info: Elaborating entity \"mux64_8\" for hierarchy \"mux64_8:inst3\"" {  } { { "fre_test.bdf" "inst3" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 48 536 680 240 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "bzq.vhd 2 1 " "Warning: Using design file bzq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bzq-behav " "Info: Found design unit 1: bzq-behav" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bzq " "Info: Found entity 1: bzq" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bzq bzq:inst1 " "Info: Elaborating entity \"bzq\" for hierarchy \"bzq:inst1\"" {  } { { "fre_test.bdf" "inst1" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 32 272 400 128 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "bena bzq.vhd(17) " "Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal \"bena\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "bzq bzq.vhd(17) " "Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal \"bzq\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "bzq bzq.vhd(13) " "Warning (10631): VHDL Process Statement warning at bzq.vhd(13): inferring latch(es) for signal or variable \"bzq\", which holds its previous value in one or more paths through the process" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[0\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[0\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[1\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[1\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[2\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[2\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[3\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[3\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[4\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[4\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[5\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[5\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[6\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[6\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[7\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[7\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[8\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[8\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[9\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[9\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[10\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[10\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[11\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[11\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "bzq\[12\] bzq.vhd(13) " "Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for \"bzq\[12\]\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}