fre_test.fit.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.424 ns register register " "Info: Estimated most critical path is register to register delay of 3.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bzq:inst1\|bzq\[6\] 1 REG LAB_X15_Y7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y7; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[6] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.443 ns) 1.273 ns bzq:inst1\|Add0~511COUT1 2 COMB LAB_X16_Y6 2 " "Info: 2: + IC(0.830 ns) + CELL(0.443 ns) = 1.273 ns; Loc. = LAB_X16_Y6; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~511COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.273 ns" { bzq:inst1|bzq[6] bzq:inst1|Add0~511COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.335 ns bzq:inst1\|Add0~503COUT1 3 COMB LAB_X16_Y6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.335 ns; Loc. = LAB_X16_Y6; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~503COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~511COUT1 bzq:inst1|Add0~503COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.397 ns bzq:inst1\|Add0~557COUT1 4 COMB LAB_X16_Y6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.397 ns; Loc. = LAB_X16_Y6; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~557COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~503COUT1 bzq:inst1|Add0~557COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.459 ns bzq:inst1\|Add0~549COUT1 5 COMB LAB_X16_Y6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.459 ns; Loc. = LAB_X16_Y6; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~549COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~557COUT1 bzq:inst1|Add0~549COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 1.658 ns bzq:inst1\|Add0~541 6 COMB LAB_X16_Y6 6 " "Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.658 ns; Loc. = LAB_X16_Y6; Fanout = 6; COMB Node = 'bzq:inst1\|Add0~541'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.199 ns" { bzq:inst1|Add0~549COUT1 bzq:inst1|Add0~541 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.763 ns bzq:inst1\|Add0~501 7 COMB LAB_X16_Y6 6 " "Info: 7: + IC(0.000 ns) + CELL(0.105 ns) = 1.763 ns; Loc. = LAB_X16_Y6; Fanout = 6; COMB Node = 'bzq:inst1\|Add0~501'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { bzq:inst1|Add0~541 bzq:inst1|Add0~501 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.868 ns bzq:inst1\|Add0~523 8 COMB LAB_X16_Y5 6 " "Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 1.868 ns; Loc. = LAB_X16_Y5; Fanout = 6; COMB Node = 'bzq:inst1\|Add0~523'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { bzq:inst1|Add0~501 bzq:inst1|Add0~523 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 2.391 ns bzq:inst1\|Add0~552 9 COMB LAB_X16_Y5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.523 ns) = 2.391 ns; Loc. = LAB_X16_Y5; Fanout = 1; COMB Node = 'bzq:inst1\|Add0~552'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.523 ns" { bzq:inst1|Add0~523 bzq:inst1|Add0~552 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.454 ns) 3.424 ns bzq:inst1\|bzq\[25\] 10 REG LAB_X17_Y6 3 " "Info: 10: + IC(0.579 ns) + CELL(0.454 ns) = 3.424 ns; Loc. = LAB_X17_Y6; Fanout = 3; REG Node = 'bzq:inst1\|bzq\[25\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.033 ns" { bzq:inst1|Add0~552 bzq:inst1|bzq[25] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.015 ns ( 58.85 % ) " "Info: Total cell delay = 2.015 ns ( 58.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.409 ns ( 41.15 % ) " "Info: Total interconnect delay = 1.409 ns ( 41.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.424 ns" { bzq:inst1|bzq[6] bzq:inst1|Add0~511COUT1 bzq:inst1|Add0~503COUT1 bzq:inst1|Add0~557COUT1 bzq:inst1|Add0~549COUT1 bzq:inst1|Add0~541 bzq:inst1|Add0~501 bzq:inst1|Add0~523 bzq:inst1|Add0~552 bzq:inst1|bzq[25] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:56:29 2008 " "Info: Processing ended: Fri May 09 10:56:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/70/quartus/work/等精度频率计设计/fre_test.fit.smsg " "Info: Generated suppressed messages file D:/altera/70/quartus/work/等精度频率计设计/fre_test.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}