fre_test.fit.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 09 10:56:25 2008 " "Info: Processing started: Fri May 09 10:56:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off fre_test -c fre_test " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fre_test -c fre_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "fre_test EP1C3T100C6 " "Info: Automatically selected device EP1C3T100C6 for design fre_test" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "152 Top " "Info: Previous placement does not exist for 152 of 152 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 6 " "Info: Pin ~nCSO~ is reserved at location 6" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 17 " "Info: Pin ~ASDO~ is reserved at location 17" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "16 16 " "Warning: No exact pin location assignment(s) for 16 pins of 16 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "START " "Info: Pin START not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { -8 504 680 8 "START" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[7\] " "Info: Pin DATA\[7\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[6\] " "Info: Pin DATA\[6\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[5\] " "Info: Pin DATA\[5\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[4\] " "Info: Pin DATA\[4\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[3\] " "Info: Pin DATA\[3\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[2\] " "Info: Pin DATA\[2\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[1\] " "Info: Pin DATA\[1\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DATA\[0\] " "Info: Pin DATA\[0\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BCLK " "Info: Pin BCLK not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 -8 160 88 "BCLK" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEL\[0\] " "Info: Pin SEL\[0\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 352 8 176 368 "SEL\[2..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEL\[1\] " "Info: Pin SEL\[1\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 352 8 176 368 "SEL\[2..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEL\[2\] " "Info: Pin SEL\[2\] not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 352 8 176 368 "SEL\[2..0\]" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CL " "Info: Pin CL not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 120 -40 128 136 "CL" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CL } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CL } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TCLK " "Info: Pin TCLK not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 296 16 184 312 "CLR" "" } } } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "TCLK Global clock in PIN 10 " "Info: Automatically promoted signal \"TCLK\" to use Global clock in PIN 10" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}