fre_test.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_TPD_RESULT" "SEL\[0\] DATA\[6\] 11.558 ns Longest " "Info: Longest tpd from source pin \"SEL\[0\]\" to destination pin \"DATA\[6\]\" is 11.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns SEL\[0\] 1 PIN PIN_38 24 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_38; Fanout = 24; PIN Node = 'SEL\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[0] } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 352 8 176 368 "SEL\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.360 ns) + CELL(0.454 ns) 5.949 ns mux64_8:inst3\|data\[6\]~3573 2 COMB LC_X17_Y6_N1 1 " "Info: 2: + IC(4.360 ns) + CELL(0.454 ns) = 5.949 ns; Loc. = LC_X17_Y6_N1; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[6\]~3573'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.814 ns" { SEL[0] mux64_8:inst3|data[6]~3573 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.088 ns) 6.368 ns mux64_8:inst3\|data\[6\]~3574 3 COMB LC_X17_Y6_N7 1 " "Info: 3: + IC(0.331 ns) + CELL(0.088 ns) = 6.368 ns; Loc. = LC_X17_Y6_N7; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[6\]~3574'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.419 ns" { mux64_8:inst3|data[6]~3573 mux64_8:inst3|data[6]~3574 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.225 ns) 7.872 ns mux64_8:inst3\|data\[6\]~3577 4 COMB LC_X15_Y5_N4 1 " "Info: 4: + IC(1.279 ns) + CELL(0.225 ns) = 7.872 ns; Loc. = LC_X15_Y5_N4; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[6\]~3577'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { mux64_8:inst3|data[6]~3574 mux64_8:inst3|data[6]~3577 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.064 ns) + CELL(1.622 ns) 11.558 ns DATA\[6\] 5 PIN PIN_89 0 " "Info: 5: + IC(2.064 ns) + CELL(1.622 ns) = 11.558 ns; Loc. = PIN_89; Fanout = 0; PIN Node = 'DATA\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.686 ns" { mux64_8:inst3|data[6]~3577 DATA[6] } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.524 ns ( 30.49 % ) " "Info: Total cell delay = 3.524 ns ( 30.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.034 ns ( 69.51 % ) " "Info: Total interconnect delay = 8.034 ns ( 69.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.558 ns" { SEL[0] mux64_8:inst3|data[6]~3573 mux64_8:inst3|data[6]~3574 mux64_8:inst3|data[6]~3577 DATA[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.558 ns" { SEL[0] SEL[0]~out0 mux64_8:inst3|data[6]~3573 mux64_8:inst3|data[6]~3574 mux64_8:inst3|data[6]~3577 DATA[6] } { 0.000ns 0.000ns 4.360ns 0.331ns 1.279ns 2.064ns } { 0.000ns 1.135ns 0.454ns 0.088ns 0.225ns 1.622ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "bzq:inst1\|bzq\[1\] CLR TCLK 2.664 ns register " "Info: th for register \"bzq:inst1\|bzq\[1\]\" (data pin = \"CLR\", clock pin = \"TCLK\") is 2.664 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK destination 6.748 ns + Longest register " "Info: + Longest clock path from clock \"TCLK\" to destination register is 6.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.345 ns) + CELL(0.088 ns) 6.748 ns bzq:inst1\|bzq\[1\] 3 REG LC_X16_Y7_N2 4 " "Info: 3: + IC(4.345 ns) + CELL(0.088 ns) = 6.748 ns; Loc. = LC_X16_Y7_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.433 ns" { inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.938 ns ( 28.72 % ) " "Info: Total cell delay = 1.938 ns ( 28.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.810 ns ( 71.28 % ) " "Info: Total interconnect delay = 4.810 ns ( 71.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.748 ns" { TCLK inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.748 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.465ns 4.345ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.084 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLR 1 PIN PIN_66 66 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 66; PIN Node = 'CLR'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 296 16 184 312 "CLR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.414 ns) 2.544 ns bzq:inst1\|bzq\[0\]~13 2 COMB LOOP LC_X16_Y7_N1 5 " "Info: 2: + IC(0.000 ns) + CELL(1.414 ns) = 2.544 ns; Loc. = LC_X16_Y7_N1; Fanout = 5; COMB LOOP Node = 'bzq:inst1\|bzq\[0\]~13'" { { "Info" "ITDB_PART_OF_SCC" "bzq:inst1\|bzq\[0\]~13 LC_X16_Y7_N1 " "Info: Loc. = LC_X16_Y7_N1; Node \"bzq:inst1\|bzq\[0\]~13\"" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[0]~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[0]~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.414 ns" { CLR bzq:inst1|bzq[0]~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.340 ns) 3.413 ns bzq:inst1\|Add0~550 3 COMB LC_X16_Y7_N5 1 " "Info: 3: + IC(0.529 ns) + CELL(0.340 ns) = 3.413 ns; Loc. = LC_X16_Y7_N5; Fanout = 1; COMB Node = 'bzq:inst1\|Add0~550'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.340 ns) 4.084 ns bzq:inst1\|bzq\[1\] 4 REG LC_X16_Y7_N2 4 " "Info: 4: + IC(0.331 ns) + CELL(0.340 ns) = 4.084 ns; Loc. = LC_X16_Y7_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "