fre_test.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "inst bzq:inst1\|bzq\[1\] TCLK 2.602 ns " "Info: Found hold time violation between source  pin or register \"inst\" and destination pin or register \"bzq:inst1\|bzq\[1\]\" for clock \"TCLK\" (Hold time is 2.602 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.606 ns + Largest " "Info: + Largest clock skew is 4.606 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK destination 6.748 ns + Longest register " "Info: + Longest clock path from clock \"TCLK\" to destination register is 6.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.345 ns) + CELL(0.088 ns) 6.748 ns bzq:inst1\|bzq\[1\] 3 REG LC_X16_Y7_N2 4 " "Info: 3: + IC(4.345 ns) + CELL(0.088 ns) = 6.748 ns; Loc. = LC_X16_Y7_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.433 ns" { inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.938 ns ( 28.72 % ) " "Info: Total cell delay = 1.938 ns ( 28.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.810 ns ( 71.28 % ) " "Info: Total interconnect delay = 4.810 ns ( 71.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.748 ns" { TCLK inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.748 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.465ns 4.345ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK source 2.142 ns - Shortest register " "Info: - Shortest clock path from clock \"TCLK\" to source register is 2.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.547 ns) 2.142 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.547 ns) = 2.142 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.012 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.29 % ) " "Info: Total cell delay = 1.677 ns ( 78.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.465 ns ( 21.71 % ) " "Info: Total interconnect delay = 0.465 ns ( 21.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { TCLK inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { TCLK TCLK~out0 inst } { 0.000ns 0.000ns 0.465ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.748 ns" { TCLK inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.748 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.465ns 4.345ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { TCLK inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { TCLK TCLK~out0 inst } { 0.000ns 0.000ns 0.465ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.831 ns - Shortest register register " "Info: - Shortest register to register delay is 1.831 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst 1 REG LC_X16_Y7_N1 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns bzq:inst1\|bzq\[0\]~13 2 COMB LOOP LC_X16_Y7_N1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X16_Y7_N1; Fanout = 5; COMB LOOP Node = 'bzq:inst1\|bzq\[0\]~13'" { { "Info" "ITDB_PART_OF_SCC" "bzq:inst1\|bzq\[0\]~13 LC_X16_Y7_N1 " "Info: Loc. = LC_X16_Y7_N1; Node \"bzq:inst1\|bzq\[0\]~13\"" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[0]~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[0]~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.291 ns" { inst bzq:inst1|bzq[0]~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.340 ns) 1.160 ns bzq:inst1\|Add0~550 3 COMB LC_X16_Y7_N5 1 " "Info: 3: + IC(0.529 ns) + CELL(0.340 ns) = 1.160 ns; Loc. = LC_X16_Y7_N5; Fanout = 1; COMB Node = 'bzq:inst1\|Add0~550'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.340 ns) 1.831 ns bzq:inst1\|bzq\[1\] 4 REG LC_X16_Y7_N2 4 " "Info: 4: + IC(0.331 ns) + CELL(0.340 ns) = 1.831 ns; Loc. = LC_X16_Y7_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.671 ns" { bzq:inst1|Add0~550 bzq:inst1|bzq[1] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.971 ns ( 53.03 % ) " "Info: Total cell delay = 0.971 ns ( 53.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.860 ns ( 46.97 % ) " "Info: Total interconnect delay = 0.860 ns ( 46.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { inst bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.831 ns" { inst bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.529ns 0.331ns } { 0.000ns 0.291ns 0.340ns 0.340ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.748 ns" { TCLK inst bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.748 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.465ns 4.345ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { TCLK inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { TCLK TCLK~out0 inst } { 0.000ns 0.000ns 0.465ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { inst bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 bzq:inst1|bzq[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.831 ns" { inst bzq:inst1|bzq[0]~13 bzq:inst1|Add0~550 bzq:inst1|bzq[1] } { 0.000ns 0.000ns 0.529ns 0.331ns } { 0.000ns 0.291ns 0.340ns 0.340ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "inst CL TCLK 3.353 ns register " "Info: tsu for register \"inst\" (data pin = \"CL\", clock pin = \"TCLK\") is 3.353 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.466 ns + Longest pin register " "Info: + Longest pin to register delay is 5.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns CL 1 PIN PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'CL'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CL } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 120 -40 128 136 "CL" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.242 ns) + CELL(0.089 ns) 5.466 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(4.242 ns) + CELL(0.089 ns) = 5.466 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.331 ns" { CL inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns ( 22.39 % ) " "Info: Total cell delay = 1.224 ns ( 22.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 77.61 % ) " "Info: Total interconnect delay = 4.242 ns ( 77.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.466 ns" { CL inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.466 ns" { CL CL~out0 inst } { 0.000ns 0.000ns 4.242ns } { 0.000ns 1.135ns 0.089ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK destination 2.142 ns - Shortest register " "Info: - Shortest clock path from clock \"TCLK\" to destination register is 2.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.547 ns) 2.142 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.547 ns) = 2.142 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.012 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.29 % ) " "Info: Total cell delay = 1.677 ns ( 78.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.465 ns ( 21.71 % ) " "Info: Total interconnect delay = 0.465 ns ( 21.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { TCLK inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { TCLK TCLK~out0 inst } { 0.000ns 0.000ns 0.465ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.466 ns" { CL inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.466 ns" { CL CL~out0 inst } { 0.000ns 0.000ns 4.242ns } { 0.000ns 1.135ns 0.089ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.142 ns" { TCLK inst } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.142 ns" { TCLK TCLK~out0 inst } { 0.000ns 0.000ns 0.465ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "TCLK DATA\[7\] bzq:inst1\|bzq\[7\] 13.828 ns register " "Info: tco from clock \"TCLK\" to destination pin \"DATA\[7\]\" through register \"bzq:inst1\|bzq\[7\]\" is 13.828 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK source 6.652 ns + Longest register " "Info: + Longest clock path from clock \"TCLK\" to source register is 6.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.249 ns) + CELL(0.088 ns) 6.652 ns bzq:inst1\|bzq\[7\] 3 REG LC_X16_Y3_N2 4 " "Info: 3: + IC(4.249 ns) + CELL(0.088 ns) = 6.652 ns; Loc. = LC_X16_Y3_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.337 ns" { inst bzq:inst1|bzq[7] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.938 ns ( 29.13 % ) " "Info: Total cell delay = 1.938 ns ( 29.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.714 ns ( 70.87 % ) " "Info: Total interconnect delay = 4.714 ns ( 70.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.652 ns" { TCLK inst bzq:inst1|bzq[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.652 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[7] } { 0.000ns 0.000ns 0.465ns 4.249ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.176 ns + Longest register pin " "Info: + Longest register to pin delay is 7.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bzq:inst1\|bzq\[7\] 1 REG LC_X16_Y3_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y3_N2; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[7] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.340 ns) 1.580 ns mux64_8:inst3\|data\[7\]~3570 2 COMB LC_X15_Y4_N3 1 " "Info: 2: + IC(1.240 ns) + CELL(0.340 ns) = 1.580 ns; Loc. = LC_X15_Y4_N3; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[7\]~3570'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { bzq:inst1|bzq[7] mux64_8:inst3|data[7]~3570 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.340 ns) 2.246 ns mux64_8:inst3\|data\[7\]~3571 3 COMB LC_X15_Y4_N4 1 " "Info: 3: + IC(0.326 ns) + CELL(0.340 ns) = 2.246 ns; Loc. = LC_X15_Y4_N4; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[7\]~3571'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.666 ns" { mux64_8:inst3|data[7]~3570 mux64_8:inst3|data[7]~3571 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.454 ns) 3.649 ns mux64_8:inst3\|data\[7\]~3572 4 COMB LC_X15_Y5_N0 1 " "Info: 4: + IC(0.949 ns) + CELL(0.454 ns) = 3.649 ns; Loc. = LC_X15_Y5_N0; Fanout = 1; COMB Node = 'mux64_8:inst3\|data\[7\]~3572'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.403 ns" { mux64_8:inst3|data[7]~3571 mux64_8:inst3|data[7]~3572 } "NODE_NAME" } } { "mux模块/mux64_8.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/mux模块/mux64_8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(1.634 ns) 7.176 ns DATA\[7\] 5 PIN PIN_56 0 " "Info: 5: + IC(1.893 ns) + CELL(1.634 ns) = 7.176 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'DATA\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.527 ns" { mux64_8:inst3|data[7]~3572 DATA[7] } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 72 720 896 88 "DATA\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns ( 38.57 % ) " "Info: Total cell delay = 2.768 ns ( 38.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.408 ns ( 61.43 % ) " "Info: Total interconnect delay = 4.408 ns ( 61.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.176 ns" { bzq:inst1|bzq[7] mux64_8:inst3|data[7]~3570 mux64_8:inst3|data[7]~3571 mux64_8:inst3|data[7]~3572 DATA[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.176 ns" { bzq:inst1|bzq[7] mux64_8:inst3|data[7]~3570 mux64_8:inst3|data[7]~3571 mux64_8:inst3|data[7]~3572 DATA[7] } { 0.000ns 1.240ns 0.326ns 0.949ns 1.893ns } { 0.000ns 0.340ns 0.340ns 0.454ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.652 ns" { TCLK inst bzq:inst1|bzq[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.652 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[7] } { 0.000ns 0.000ns 0.465ns 4.249ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.176 ns" { bzq:inst1|bzq[7] mux64_8:inst3|data[7]~3570 mux64_8:inst3|data[7]~3571 mux64_8:inst3|data[7]~3572 DATA[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.176 ns" { bzq:inst1|bzq[7] mux64_8:inst3|data[7]~3570 mux64_8:inst3|data[7]~3571 mux64_8:inst3|data[7]~3572 DATA[7] } { 0.000ns 1.240ns 0.326ns 0.949ns 1.893ns } { 0.000ns 0.340ns 0.340ns 0.454ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}