📄 fre_test.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "inst " "Info: Detected ripple clock \"inst\" as buffer" { } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "inst" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "TCLK register bzq:inst1\|bzq\[11\] register bzq:inst1\|bzq\[20\] 226.96 MHz 4.406 ns Internal " "Info: Clock \"TCLK\" has Internal fmax of 226.96 MHz between source register \"bzq:inst1\|bzq\[11\]\" and destination register \"bzq:inst1\|bzq\[20\]\" (period= 4.406 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.548 ns + Longest register register " "Info: + Longest register to register delay is 3.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bzq:inst1\|bzq\[11\] 1 REG LC_X17_Y4_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y4_N7; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[11\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq:inst1|bzq[11] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.443 ns) 1.384 ns bzq:inst1\|Add0~533COUT1 2 COMB LC_X16_Y6_N5 2 " "Info: 2: + IC(0.941 ns) + CELL(0.443 ns) = 1.384 ns; Loc. = LC_X16_Y6_N5; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~533COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.384 ns" { bzq:inst1|bzq[11] bzq:inst1|Add0~533COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.446 ns bzq:inst1\|Add0~525COUT1 3 COMB LC_X16_Y6_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.446 ns; Loc. = LC_X16_Y6_N6; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~525COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~533COUT1 bzq:inst1|Add0~525COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.508 ns bzq:inst1\|Add0~517COUT1 4 COMB LC_X16_Y6_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.508 ns; Loc. = LC_X16_Y6_N7; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~517COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~525COUT1 bzq:inst1|Add0~517COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.570 ns bzq:inst1\|Add0~509COUT1 5 COMB LC_X16_Y6_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.570 ns; Loc. = LC_X16_Y6_N8; Fanout = 2; COMB Node = 'bzq:inst1\|Add0~509COUT1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { bzq:inst1|Add0~517COUT1 bzq:inst1|Add0~509COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 1.769 ns bzq:inst1\|Add0~501 6 COMB LC_X16_Y6_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.769 ns; Loc. = LC_X16_Y6_N9; Fanout = 6; COMB Node = 'bzq:inst1\|Add0~501'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.199 ns" { bzq:inst1|Add0~509COUT1 bzq:inst1|Add0~501 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 2.292 ns bzq:inst1\|Add0~522 7 COMB LC_X16_Y5_N4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.523 ns) = 2.292 ns; Loc. = LC_X16_Y5_N4; Fanout = 1; COMB Node = 'bzq:inst1\|Add0~522'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.523 ns" { bzq:inst1|Add0~501 bzq:inst1|Add0~522 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.340 ns) 3.548 ns bzq:inst1\|bzq\[20\] 8 REG LC_X17_Y7_N2 3 " "Info: 8: + IC(0.916 ns) + CELL(0.340 ns) = 3.548 ns; Loc. = LC_X17_Y7_N2; Fanout = 3; REG Node = 'bzq:inst1\|bzq\[20\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { bzq:inst1|Add0~522 bzq:inst1|bzq[20] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.691 ns ( 47.66 % ) " "Info: Total cell delay = 1.691 ns ( 47.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.857 ns ( 52.34 % ) " "Info: Total interconnect delay = 1.857 ns ( 52.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { bzq:inst1|bzq[11] bzq:inst1|Add0~533COUT1 bzq:inst1|Add0~525COUT1 bzq:inst1|Add0~517COUT1 bzq:inst1|Add0~509COUT1 bzq:inst1|Add0~501 bzq:inst1|Add0~522 bzq:inst1|bzq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { bzq:inst1|bzq[11] bzq:inst1|Add0~533COUT1 bzq:inst1|Add0~525COUT1 bzq:inst1|Add0~517COUT1 bzq:inst1|Add0~509COUT1 bzq:inst1|Add0~501 bzq:inst1|Add0~522 bzq:inst1|bzq[20] } { 0.000ns 0.941ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.916ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.523ns 0.340ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.030 ns - Smallest " "Info: - Smallest clock skew is 0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK destination 6.737 ns + Shortest register " "Info: + Shortest clock path from clock \"TCLK\" to destination register is 6.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.334 ns) + CELL(0.088 ns) 6.737 ns bzq:inst1\|bzq\[20\] 3 REG LC_X17_Y7_N2 3 " "Info: 3: + IC(4.334 ns) + CELL(0.088 ns) = 6.737 ns; Loc. = LC_X17_Y7_N2; Fanout = 3; REG Node = 'bzq:inst1\|bzq\[20\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.422 ns" { inst bzq:inst1|bzq[20] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.938 ns ( 28.77 % ) " "Info: Total cell delay = 1.938 ns ( 28.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.799 ns ( 71.23 % ) " "Info: Total interconnect delay = 4.799 ns ( 71.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.737 ns" { TCLK inst bzq:inst1|bzq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.737 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[20] } { 0.000ns 0.000ns 0.465ns 4.334ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TCLK source 6.707 ns - Longest register " "Info: - Longest clock path from clock \"TCLK\" to source register is 6.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns TCLK 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'TCLK'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TCLK } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns inst 2 REG LC_X16_Y7_N1 34 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X16_Y7_N1; Fanout = 34; REG Node = 'inst'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { TCLK inst } "NODE_NAME" } } { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 104 168 232 184 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.304 ns) + CELL(0.088 ns) 6.707 ns bzq:inst1\|bzq\[11\] 3 REG LC_X17_Y4_N7 4 " "Info: 3: + IC(4.304 ns) + CELL(0.088 ns) = 6.707 ns; Loc. = LC_X17_Y4_N7; Fanout = 4; REG Node = 'bzq:inst1\|bzq\[11\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.392 ns" { inst bzq:inst1|bzq[11] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.938 ns ( 28.90 % ) " "Info: Total cell delay = 1.938 ns ( 28.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.769 ns ( 71.10 % ) " "Info: Total interconnect delay = 4.769 ns ( 71.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { TCLK inst bzq:inst1|bzq[11] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.707 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[11] } { 0.000ns 0.000ns 0.465ns 4.304ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.737 ns" { TCLK inst bzq:inst1|bzq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.737 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[20] } { 0.000ns 0.000ns 0.465ns 4.334ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { TCLK inst bzq:inst1|bzq[11] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.707 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[11] } { 0.000ns 0.000ns 0.465ns 4.304ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.888 ns + " "Info: + Micro setup delay of destination is 0.888 ns" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { bzq:inst1|bzq[11] bzq:inst1|Add0~533COUT1 bzq:inst1|Add0~525COUT1 bzq:inst1|Add0~517COUT1 bzq:inst1|Add0~509COUT1 bzq:inst1|Add0~501 bzq:inst1|Add0~522 bzq:inst1|bzq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { bzq:inst1|bzq[11] bzq:inst1|Add0~533COUT1 bzq:inst1|Add0~525COUT1 bzq:inst1|Add0~517COUT1 bzq:inst1|Add0~509COUT1 bzq:inst1|Add0~501 bzq:inst1|Add0~522 bzq:inst1|bzq[20] } { 0.000ns 0.941ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.916ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.523ns 0.340ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.737 ns" { TCLK inst bzq:inst1|bzq[20] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.737 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[20] } { 0.000ns 0.000ns 0.465ns 4.334ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { TCLK inst bzq:inst1|bzq[11] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.707 ns" { TCLK TCLK~out0 inst bzq:inst1|bzq[11] } { 0.000ns 0.000ns 0.465ns 4.304ns } { 0.000ns 1.130ns 0.720ns 0.088ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "TCLK 31 " "Warning: Circuit may not operate. Detected 31 non-operational path(s) clocked by clock \"TCLK\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
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