fre_test.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[23\] " "Warning: Node \"bzq:inst1\|bzq\[23\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[22\] " "Warning: Node \"bzq:inst1\|bzq\[22\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[15\] " "Warning: Node \"bzq:inst1\|bzq\[15\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[10\] " "Warning: Node \"bzq:inst1\|bzq\[10\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[14\] " "Warning: Node \"bzq:inst1\|bzq\[14\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[7\] " "Warning: Node \"bzq:inst1\|bzq\[7\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[5\] " "Warning: Node \"bzq:inst1\|bzq\[5\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[6\] " "Warning: Node \"bzq:inst1\|bzq\[6\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[31\] " "Warning: Node \"bzq:inst1\|bzq\[31\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[20\] " "Warning: Node \"bzq:inst1\|bzq\[20\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[21\] " "Warning: Node \"bzq:inst1\|bzq\[21\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[13\] " "Warning: Node \"bzq:inst1\|bzq\[13\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[30\] " "Warning: Node \"bzq:inst1\|bzq\[30\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[25\] " "Warning: Node \"bzq:inst1\|bzq\[25\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[29\] " "Warning: Node \"bzq:inst1\|bzq\[29\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[12\] " "Warning: Node \"bzq:inst1\|bzq\[12\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[4\] " "Warning: Node \"bzq:inst1\|bzq\[4\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[28\] " "Warning: Node \"bzq:inst1\|bzq\[28\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[19\] " "Warning: Node \"bzq:inst1\|bzq\[19\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[11\] " "Warning: Node \"bzq:inst1\|bzq\[11\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[3\] " "Warning: Node \"bzq:inst1\|bzq\[3\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[27\] " "Warning: Node \"bzq:inst1\|bzq\[27\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[18\] " "Warning: Node \"bzq:inst1\|bzq\[18\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[2\] " "Warning: Node \"bzq:inst1\|bzq\[2\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[26\] " "Warning: Node \"bzq:inst1\|bzq\[26\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[17\] " "Warning: Node \"bzq:inst1\|bzq\[17\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[9\] " "Warning: Node \"bzq:inst1\|bzq\[9\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[1\] " "Warning: Node \"bzq:inst1\|bzq\[1\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[16\] " "Warning: Node \"bzq:inst1\|bzq\[16\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[8\] " "Warning: Node \"bzq:inst1\|bzq\[8\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq:inst1\|bzq\[24\] " "Warning: Node \"bzq:inst1\|bzq\[24\]\" is a latch" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "bzq:inst1\|bzq\[0\]~13 " "Warning: Node \"bzq:inst1\|bzq\[0\]~13\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq.vhd" 13 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "TCLK " "Info: Assuming node \"TCLK\" is an undefined clock" {  } { { "fre_test.bdf" "" { Schematic "D:/altera/70/quartus/work/等精度频率计设计/fre_test.bdf" { { 200 -24 144 216 "TCLK" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}