bzq.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_TCO_RESULT" "bena bzq\[2\] bzq\[2\]\$latch 6.537 ns register " "Info: tco from clock \"bena\" to destination pin \"bzq\[2\]\" through register \"bzq\[2\]\$latch\" is 6.537 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bena source 2.179 ns + Longest register " "Info: + Longest clock path from clock \"bena\" to source register is 2.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.088 ns) 2.179 ns bzq\[2\]\$latch 2 REG LC_X22_Y11_N0 4 " "Info: 2: + IC(0.961 ns) + CELL(0.088 ns) = 2.179 ns; Loc. = LC_X22_Y11_N0; Fanout = 4; REG Node = 'bzq\[2\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.049 ns" { bena bzq[2]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns ( 55.90 % ) " "Info: Total cell delay = 1.218 ns ( 55.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.961 ns ( 44.10 % ) " "Info: Total interconnect delay = 0.961 ns ( 44.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.179 ns" { bena bzq[2]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.179 ns" { bena bena~out0 bzq[2]$latch } { 0.000ns 0.000ns 0.961ns } { 0.000ns 1.130ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.358 ns + Longest register pin " "Info: + Longest register to pin delay is 4.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bzq\[2\]\$latch 1 REG LC_X22_Y11_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N0; Fanout = 4; REG Node = 'bzq\[2\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[2]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.724 ns) + CELL(1.634 ns) 4.358 ns bzq\[2\] 2 PIN PIN_5 0 " "Info: 2: + IC(2.724 ns) + CELL(1.634 ns) = 4.358 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'bzq\[2\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.358 ns" { bzq[2]$latch bzq[2] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 37.49 % ) " "Info: Total cell delay = 1.634 ns ( 37.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.724 ns ( 62.51 % ) " "Info: Total interconnect delay = 2.724 ns ( 62.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.358 ns" { bzq[2]$latch bzq[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.358 ns" { bzq[2]$latch bzq[2] } { 0.000ns 2.724ns } { 0.000ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.179 ns" { bena bzq[2]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.179 ns" { bena bena~out0 bzq[2]$latch } { 0.000ns 0.000ns 0.961ns } { 0.000ns 1.130ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.358 ns" { bzq[2]$latch bzq[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.358 ns" { bzq[2]$latch bzq[2] } { 0.000ns 2.724ns } { 0.000ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clr bzq\[0\] 9.729 ns Longest " "Info: Longest tpd from source pin \"clr\" to destination pin \"bzq\[0\]\" is 9.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clr 1 PIN PIN_73 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_73; Fanout = 33; PIN Node = 'clr'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.038 ns) 6.168 ns bzq\[0\]\$latch~13 2 COMB LOOP LC_X23_Y10_N3 5 " "Info: 2: + IC(0.000 ns) + CELL(5.038 ns) = 6.168 ns; Loc. = LC_X23_Y10_N3; Fanout = 5; COMB LOOP Node = 'bzq\[0\]\$latch~13'" { { "Info" "ITDB_PART_OF_SCC" "bzq\[0\]\$latch~13 LC_X23_Y10_N3 " "Info: Loc. = LC_X23_Y10_N3; Node \"bzq\[0\]\$latch~13\"" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.038 ns" { clr bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.939 ns) + CELL(1.622 ns) 9.729 ns bzq\[0\] 3 PIN PIN_41 0 " "Info: 3: + IC(1.939 ns) + CELL(1.622 ns) = 9.729 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'bzq\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.561 ns" { bzq[0]$latch~13 bzq[0] } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.790 ns ( 80.07 % ) " "Info: Total cell delay = 7.790 ns ( 80.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.939 ns ( 19.93 % ) " "Info: Total interconnect delay = 1.939 ns ( 19.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.729 ns" { clr bzq[0]$latch~13 bzq[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.729 ns" { clr clr~out0 bzq[0]$latch~13 bzq[0] } { 0.000ns 0.000ns 0.000ns 1.939ns } { 0.000ns 1.130ns 5.038ns 1.622ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "bzq\[1\]\$latch bena bena -2.169 ns register " "Info: th for register \"bzq\[1\]\$latch\" (data pin = \"bena\", clock pin = \"bena\") is -2.169 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bena destination 2.175 ns + Longest register " "Info: + Longest clock path from clock \"bena\" to destination register is 2.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.957 ns) + CELL(0.088 ns) 2.175 ns bzq\[1\]\$latch 2 REG LC_X22_Y11_N4 4 " "Info: 2: + IC(0.957 ns) + CELL(0.088 ns) = 2.175 ns; Loc. = LC_X22_Y11_N4; Fanout = 4; REG Node = 'bzq\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.045 ns" { bena bzq[1]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns ( 56.00 % ) " "Info: Total cell delay = 1.218 ns ( 56.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.957 ns ( 44.00 % ) " "Info: Total interconnect delay = 0.957 ns ( 44.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.175 ns" { bena bzq[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.175 ns" { bena bena~out0 bzq[1]$latch } { 0.000ns 0.000ns 0.957ns } { 0.000ns 1.130ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.344 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.151 ns) 2.281 ns bzq\[0\]\$latch~13 2 COMB LOOP LC_X23_Y10_N3 5 " "Info: 2: + IC(0.000 ns) + CELL(1.151 ns) = 2.281 ns; Loc. = LC_X23_Y10_N3; Fanout = 5; COMB LOOP Node = 'bzq\[0\]\$latch~13'" { { "Info" "ITDB_PART_OF_SCC" "bzq\[0\]\$latch~13 LC_X23_Y10_N3 " "Info: Loc. = LC_X23_Y10_N3; Node \"bzq\[0\]\$latch~13\"" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.151 ns" { bena bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.454 ns) 3.675 ns Add0~183 3 COMB LC_X22_Y11_N5 1 " "Info: 3: + IC(0.940 ns) + CELL(0.454 ns) = 3.675 ns; Loc. = LC_X22_Y11_N5; Fanout = 1; COMB Node = 'Add0~183'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.394 ns" { bzq[0]$latch~13 Add0~183 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.340 ns) 4.344 ns bzq\[1\]\$latch 4 REG LC_X22_Y11_N4 4 " "Info: 4: + IC(0.329 ns) + CELL(0.340 ns) = 4.344 ns; Loc. = LC_X22_Y11_N4; Fanout = 4; REG Node = 'bzq\[1\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.669 ns" { Add0~183 bzq[1]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.075 ns ( 70.79 % ) " "Info: Total cell delay = 3.075 ns ( 70.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns ( 29.21 % ) " "Info: Total interconnect delay = 1.269 ns ( 29.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.344 ns" { bena bzq[0]$latch~13 Add0~183 bzq[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.344 ns" { bena bena~out0 bzq[0]$latch~13 Add0~183 bzq[1]$latch } { 0.000ns 0.000ns 0.000ns 0.940ns 0.329ns } { 0.000ns 1.130ns 1.151ns 0.454ns 0.340ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.175 ns" { bena bzq[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.175 ns" { bena bena~out0 bzq[1]$latch } { 0.000ns 0.000ns 0.957ns } { 0.000ns 1.130ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.344 ns" { bena bzq[0]$latch~13 Add0~183 bzq[1]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.344 ns" { bena bena~out0 bzq[0]$latch~13 Add0~183 bzq[1]$latch } { 0.000ns 0.000ns 0.000ns 0.940ns 0.329ns } { 0.000ns 1.130ns 1.151ns 0.454ns 0.340ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 35 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:10:32 2008 " "Info: Processing ended: Fri May 09 10:10:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}