bzq.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "bzq\[0\]\$latch~13 " "Warning: Node \"bzq\[0\]\$latch~13\"" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "bena " "Info: Assuming node \"bena\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "bena register bzq\[14\]\$latch register bzq\[26\]\$latch 240.38 MHz 4.16 ns Internal " "Info: Clock \"bena\" has Internal fmax of 240.38 MHz between source register \"bzq\[14\]\$latch\" and destination register \"bzq\[26\]\$latch\" (period= 4.16 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.245 ns + Longest register register " "Info: + Longest register to register delay is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bzq\[14\]\$latch 1 REG LC_X21_Y9_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y9_N7; Fanout = 4; REG Node = 'bzq\[14\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[14]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.326 ns) 1.241 ns Add0~210 2 COMB LC_X22_Y10_N8 2 " "Info: 2: + IC(0.915 ns) + CELL(0.326 ns) = 1.241 ns; Loc. = LC_X22_Y10_N8; Fanout = 2; COMB Node = 'Add0~210'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.241 ns" { bzq[14]$latch Add0~210 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 1.450 ns Add0~212 3 COMB LC_X22_Y10_N9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.209 ns) = 1.450 ns; Loc. = LC_X22_Y10_N9; Fanout = 6; COMB Node = 'Add0~212'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.209 ns" { Add0~210 Add0~212 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.555 ns Add0~222 4 COMB LC_X22_Y9_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.105 ns) = 1.555 ns; Loc. = LC_X22_Y9_N4; Fanout = 6; COMB Node = 'Add0~222'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { Add0~212 Add0~222 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 1.715 ns Add0~232 5 COMB LC_X22_Y9_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.160 ns) = 1.715 ns; Loc. = LC_X22_Y9_N9; Fanout = 6; COMB Node = 'Add0~232'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { Add0~222 Add0~232 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 2.238 ns Add0~233 6 COMB LC_X22_Y8_N0 1 " "Info: 6: + IC(0.000 ns) + CELL(0.523 ns) = 2.238 ns; Loc. = LC_X22_Y8_N0; Fanout = 1; COMB Node = 'Add0~233'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.523 ns" { Add0~232 Add0~233 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.088 ns) 3.245 ns bzq\[26\]\$latch 7 REG LC_X21_Y9_N8 4 " "Info: 7: + IC(0.919 ns) + CELL(0.088 ns) = 3.245 ns; Loc. = LC_X21_Y9_N8; Fanout = 4; REG Node = 'bzq\[26\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.007 ns" { Add0~233 bzq[26]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.411 ns ( 43.48 % ) " "Info: Total cell delay = 1.411 ns ( 43.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.834 ns ( 56.52 % ) " "Info: Total interconnect delay = 1.834 ns ( 56.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.245 ns" { bzq[14]$latch Add0~210 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.245 ns" { bzq[14]$latch Add0~210 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } { 0.000ns 0.915ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns } { 0.000ns 0.326ns 0.209ns 0.105ns 0.160ns 0.523ns 0.088ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.035 ns - Smallest " "Info: - Smallest clock skew is -0.035 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bena destination 2.253 ns + Shortest register " "Info: + Shortest clock path from clock \"bena\" to destination register is 2.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.225 ns) 2.253 ns bzq\[26\]\$latch 2 REG LC_X21_Y9_N8 4 " "Info: 2: + IC(0.898 ns) + CELL(0.225 ns) = 2.253 ns; Loc. = LC_X21_Y9_N8; Fanout = 4; REG Node = 'bzq\[26\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.355 ns ( 60.14 % ) " "Info: Total cell delay = 1.355 ns ( 60.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.898 ns ( 39.86 % ) " "Info: Total interconnect delay = 0.898 ns ( 39.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.253 ns" { bena bena~out0 bzq[26]$latch } { 0.000ns 0.000ns 0.898ns } { 0.000ns 1.130ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bena source 2.288 ns - Longest register " "Info: - Longest clock path from clock \"bena\" to source register is 2.288 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.088 ns) 2.288 ns bzq\[14\]\$latch 2 REG LC_X21_Y9_N7 4 " "Info: 2: + IC(1.070 ns) + CELL(0.088 ns) = 2.288 ns; Loc. = LC_X21_Y9_N7; Fanout = 4; REG Node = 'bzq\[14\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.158 ns" { bena bzq[14]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns ( 53.23 % ) " "Info: Total cell delay = 1.218 ns ( 53.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.070 ns ( 46.77 % ) " "Info: Total interconnect delay = 1.070 ns ( 46.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.288 ns" { bena bzq[14]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.288 ns" { bena bena~out0 bzq[14]$latch } { 0.000ns 0.000ns 1.070ns } { 0.000ns 1.130ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.253 ns" { bena bena~out0 bzq[26]$latch } { 0.000ns 0.000ns 0.898ns } { 0.000ns 1.130ns 0.225ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.288 ns" { bena bzq[14]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.288 ns" { bena bena~out0 bzq[14]$latch } { 0.000ns 0.000ns 1.070ns } { 0.000ns 1.130ns 0.088ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.880 ns + " "Info: + Micro setup delay of destination is 0.880 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.245 ns" { bzq[14]$latch Add0~210 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.245 ns" { bzq[14]$latch Add0~210 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } { 0.000ns 0.915ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns } { 0.000ns 0.326ns 0.209ns 0.105ns 0.160ns 0.523ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.253 ns" { bena bena~out0 bzq[26]$latch } { 0.000ns 0.000ns 0.898ns } { 0.000ns 1.130ns 0.225ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.288 ns" { bena bzq[14]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.288 ns" { bena bena~out0 bzq[14]$latch } { 0.000ns 0.000ns 1.070ns } { 0.000ns 1.130ns 0.088ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "bzq\[26\]\$latch clr bena 8.623 ns register " "Info: tsu for register \"bzq\[26\]\$latch\" (data pin = \"clr\", clock pin = \"bena\") is 8.623 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.996 ns + Longest pin register " "Info: + Longest pin to register delay is 9.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clr 1 PIN PIN_73 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_73; Fanout = 33; PIN Node = 'clr'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.038 ns) 6.168 ns bzq\[0\]\$latch~13 2 COMB LOOP LC_X23_Y10_N3 5 " "Info: 2: + IC(0.000 ns) + CELL(5.038 ns) = 6.168 ns; Loc. = LC_X23_Y10_N3; Fanout = 5; COMB LOOP Node = 'bzq\[0\]\$latch~13'" { { "Info" "ITDB_PART_OF_SCC" "bzq\[0\]\$latch~13 LC_X23_Y10_N3 " "Info: Loc. = LC_X23_Y10_N3; Node \"bzq\[0\]\$latch~13\"" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.038 ns" { clr bzq[0]$latch~13 } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.443 ns) 7.551 ns Add0~184COUT1 3 COMB LC_X22_Y11_N5 2 " "Info: 3: + IC(0.940 ns) + CELL(0.443 ns) = 7.551 ns; Loc. = LC_X22_Y11_N5; Fanout = 2; COMB Node = 'Add0~184COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.383 ns" { bzq[0]$latch~13 Add0~184COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 7.613 ns Add0~186COUT1 4 COMB LC_X22_Y11_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 7.613 ns; Loc. = LC_X22_Y11_N6; Fanout = 2; COMB Node = 'Add0~186COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { Add0~184COUT1 Add0~186COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 7.675 ns Add0~188COUT1 5 COMB LC_X22_Y11_N7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 7.675 ns; Loc. = LC_X22_Y11_N7; Fanout = 2; COMB Node = 'Add0~188COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { Add0~186COUT1 Add0~188COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 7.737 ns Add0~190COUT1 6 COMB LC_X22_Y11_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 7.737 ns; Loc. = LC_X22_Y11_N8; Fanout = 2; COMB Node = 'Add0~190COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { Add0~188COUT1 Add0~190COUT1 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 7.936 ns Add0~192 7 COMB LC_X22_Y11_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.199 ns) = 7.936 ns; Loc. = LC_X22_Y11_N9; Fanout = 6; COMB Node = 'Add0~192'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.199 ns" { Add0~190COUT1 Add0~192 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 8.041 ns Add0~202 8 COMB LC_X22_Y10_N4 6 " "Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 8.041 ns; Loc. = LC_X22_Y10_N4; Fanout = 6; COMB Node = 'Add0~202'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { Add0~192 Add0~202 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 8.201 ns Add0~212 9 COMB LC_X22_Y10_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.160 ns) = 8.201 ns; Loc. = LC_X22_Y10_N9; Fanout = 6; COMB Node = 'Add0~212'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { Add0~202 Add0~212 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 8.306 ns Add0~222 10 COMB LC_X22_Y9_N4 6 " "Info: 10: + IC(0.000 ns) + CELL(0.105 ns) = 8.306 ns; Loc. = LC_X22_Y9_N4; Fanout = 6; COMB Node = 'Add0~222'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { Add0~212 Add0~222 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 8.466 ns Add0~232 11 COMB LC_X22_Y9_N9 6 " "Info: 11: + IC(0.000 ns) + CELL(0.160 ns) = 8.466 ns; Loc. = LC_X22_Y9_N9; Fanout = 6; COMB Node = 'Add0~232'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { Add0~222 Add0~232 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 8.989 ns Add0~233 12 COMB LC_X22_Y8_N0 1 " "Info: 12: + IC(0.000 ns) + CELL(0.523 ns) = 8.989 ns; Loc. = LC_X22_Y8_N0; Fanout = 1; COMB Node = 'Add0~233'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.523 ns" { Add0~232 Add0~233 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.088 ns) 9.996 ns bzq\[26\]\$latch 13 REG LC_X21_Y9_N8 4 " "Info: 13: + IC(0.919 ns) + CELL(0.088 ns) = 9.996 ns; Loc. = LC_X21_Y9_N8; Fanout = 4; REG Node = 'bzq\[26\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.007 ns" { Add0~233 bzq[26]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.137 ns ( 81.40 % ) " "Info: Total cell delay = 8.137 ns ( 81.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.859 ns ( 18.60 % ) " "Info: Total interconnect delay = 1.859 ns ( 18.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.996 ns" { clr bzq[0]$latch~13 Add0~184COUT1 Add0~186COUT1 Add0~188COUT1 Add0~190COUT1 Add0~192 Add0~202 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.996 ns" { clr clr~out0 bzq[0]$latch~13 Add0~184COUT1 Add0~186COUT1 Add0~188COUT1 Add0~190COUT1 Add0~192 Add0~202 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } { 0.000ns 0.000ns 0.000ns 0.940ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns } { 0.000ns 1.130ns 5.038ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.105ns 0.160ns 0.105ns 0.160ns 0.523ns 0.088ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.880 ns + " "Info: + Micro setup delay of destination is 0.880 ns" {  } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bena destination 2.253 ns - Shortest register " "Info: - Shortest clock path from clock \"bena\" to destination register is 2.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns bena 1 CLK PIN_10 33 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 33; CLK Node = 'bena'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { bena } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.225 ns) 2.253 ns bzq\[26\]\$latch 2 REG LC_X21_Y9_N8 4 " "Info: 2: + IC(0.898 ns) + CELL(0.225 ns) = 2.253 ns; Loc. = LC_X21_Y9_N8; Fanout = 4; REG Node = 'bzq\[26\]\$latch'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.355 ns ( 60.14 % ) " "Info: Total cell delay = 1.355 ns ( 60.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.898 ns ( 39.86 % ) " "Info: Total interconnect delay = 0.898 ns ( 39.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.253 ns" { bena bena~out0 bzq[26]$latch } { 0.000ns 0.000ns 0.898ns } { 0.000ns 1.130ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.996 ns" { clr bzq[0]$latch~13 Add0~184COUT1 Add0~186COUT1 Add0~188COUT1 Add0~190COUT1 Add0~192 Add0~202 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.996 ns" { clr clr~out0 bzq[0]$latch~13 Add0~184COUT1 Add0~186COUT1 Add0~188COUT1 Add0~190COUT1 Add0~192 Add0~202 Add0~212 Add0~222 Add0~232 Add0~233 bzq[26]$latch } { 0.000ns 0.000ns 0.000ns 0.940ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.919ns } { 0.000ns 1.130ns 5.038ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.105ns 0.160ns 0.105ns 0.160ns 0.523ns 0.088ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.253 ns" { bena bzq[26]$latch } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.253 ns" { bena bena~out0 bzq[26]$latch } { 0.000ns 0.000ns 0.898ns } { 0.000ns 1.130ns 0.225ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}