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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 09 10:10:31 2008 " "Info: Processing started: Fri May 09 10:10:31 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off bzq -c bzq --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bzq -c bzq --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[1\]\$latch " "Warning: Node \"bzq\[1\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[2\]\$latch " "Warning: Node \"bzq\[2\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[3\]\$latch " "Warning: Node \"bzq\[3\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[4\]\$latch " "Warning: Node \"bzq\[4\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[5\]\$latch " "Warning: Node \"bzq\[5\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[6\]\$latch " "Warning: Node \"bzq\[6\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[7\]\$latch " "Warning: Node \"bzq\[7\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[8\]\$latch " "Warning: Node \"bzq\[8\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[9\]\$latch " "Warning: Node \"bzq\[9\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[10\]\$latch " "Warning: Node \"bzq\[10\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[11\]\$latch " "Warning: Node \"bzq\[11\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[12\]\$latch " "Warning: Node \"bzq\[12\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[13\]\$latch " "Warning: Node \"bzq\[13\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[14\]\$latch " "Warning: Node \"bzq\[14\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[15\]\$latch " "Warning: Node \"bzq\[15\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[16\]\$latch " "Warning: Node \"bzq\[16\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[17\]\$latch " "Warning: Node \"bzq\[17\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[18\]\$latch " "Warning: Node \"bzq\[18\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[19\]\$latch " "Warning: Node \"bzq\[19\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[20\]\$latch " "Warning: Node \"bzq\[20\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[21\]\$latch " "Warning: Node \"bzq\[21\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[22\]\$latch " "Warning: Node \"bzq\[22\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[23\]\$latch " "Warning: Node \"bzq\[23\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[24\]\$latch " "Warning: Node \"bzq\[24\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[25\]\$latch " "Warning: Node \"bzq\[25\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[26\]\$latch " "Warning: Node \"bzq\[26\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[27\]\$latch " "Warning: Node \"bzq\[27\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[28\]\$latch " "Warning: Node \"bzq\[28\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[29\]\$latch " "Warning: Node \"bzq\[29\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[30\]\$latch " "Warning: Node \"bzq\[30\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "bzq\[31\]\$latch " "Warning: Node \"bzq\[31\]\$latch\" is a latch" { } { { "bzq.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/bzq模块/bzq.vhd" 13 0 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
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