bzq.map.rpt

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

;     -- normal mode                          ; 33    ;
;     -- arithmetic mode                      ; 30    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; Total logic cells in carry chains           ; 31    ;
; I/O pins                                    ; 0     ;
; Maximum fan-out node                        ; bena  ;
; Maximum fan-out                             ; 32    ;
; Total fan-out                               ; 221   ;
; Average fan-out                             ; 2.26  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |bzq                       ; 63 (63)     ; 0            ; 0           ; 0    ; 0            ; 63 (63)      ; 0 (0)             ; 0 (0)            ; 31 (31)         ; 0 (0)      ; |bzq                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; bzq[0]$latch                                        ; bena                ; yes                    ;
; bzq[1]$latch                                        ; bena                ; yes                    ;
; bzq[2]$latch                                        ; bena                ; yes                    ;
; bzq[3]$latch                                        ; bena                ; yes                    ;
; bzq[4]$latch                                        ; bena                ; yes                    ;
; bzq[5]$latch                                        ; bena                ; yes                    ;
; bzq[6]$latch                                        ; bena                ; yes                    ;
; bzq[7]$latch                                        ; bena                ; yes                    ;
; bzq[8]$latch                                        ; bena                ; yes                    ;
; bzq[9]$latch                                        ; bena                ; yes                    ;
; bzq[10]$latch                                       ; bena                ; yes                    ;
; bzq[11]$latch                                       ; bena                ; yes                    ;
; bzq[12]$latch                                       ; bena                ; yes                    ;
; bzq[13]$latch                                       ; bena                ; yes                    ;
; bzq[14]$latch                                       ; bena                ; yes                    ;
; bzq[15]$latch                                       ; bena                ; yes                    ;
; bzq[16]$latch                                       ; bena                ; yes                    ;
; bzq[17]$latch                                       ; bena                ; yes                    ;
; bzq[18]$latch                                       ; bena                ; yes                    ;
; bzq[19]$latch                                       ; bena                ; yes                    ;
; bzq[20]$latch                                       ; bena                ; yes                    ;
; bzq[21]$latch                                       ; bena                ; yes                    ;
; bzq[22]$latch                                       ; bena                ; yes                    ;
; bzq[23]$latch                                       ; bena                ; yes                    ;
; bzq[24]$latch                                       ; bena                ; yes                    ;
; bzq[25]$latch                                       ; bena                ; yes                    ;
; bzq[26]$latch                                       ; bena                ; yes                    ;
; bzq[27]$latch                                       ; bena                ; yes                    ;
; bzq[28]$latch                                       ; bena                ; yes                    ;
; bzq[29]$latch                                       ; bena                ; yes                    ;
; bzq[30]$latch                                       ; bena                ; yes                    ;
; bzq[31]$latch                                       ; bena                ; yes                    ;
; Number of user-specified and inferred latches = 32  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri May 09 10:10:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bzq -c bzq
Info: Found 2 design units, including 1 entities, in source file bzq.vhd
    Info: Found design unit 1: bzq-behav
    Info: Found entity 1: bzq
Info: Elaborating entity "bzq" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal "bena" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal "bzq" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at bzq.vhd(13): inferring latch(es) for signal or variable "bzq", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[0]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[1]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[2]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[3]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[4]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[5]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[6]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[7]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[8]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[9]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[10]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[11]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[12]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[13]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[14]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[15]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[16]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[17]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[18]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[19]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[20]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[21]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[22]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[23]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[24]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[25]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[26]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[27]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[28]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[29]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[30]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[31]"
Info: Implemented 98 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 32 output pins
    Info: Implemented 63 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 132 megabytes of memory during processing
    Info: Processing ended: Fri May 09 10:10:08 2008
    Info: Elapsed time: 00:00:02