mux64_8.vhd

来自「等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity mux64_8 is
port (a,b,c,d,e,f,g,h:in std_logic_vector(7 downto 0);
      sel:in std_logic_vector(2 downto 0);
     data:out std_logic_vector(7 downto 0));
end mux64_8;
architecture behav of mux64_8 is
begin
  data<=a when sel="000" else 
        b when sel="001" else
        c when sel="010" else
        d when sel="011" else 
        e when sel="100" else
        f when sel="101" else  
        g when sel="110" else 
        h ;   
end behav;