tf.tan.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "tclk register tsq\[0\]~reg0 register tsq\[31\]~reg0 365.76 MHz 2.734 ns Internal " "Info: Clock \"tclk\" has Internal fmax of 365.76 MHz between source register \"tsq\[0\]~reg0\" and destination register \"tsq\[31\]~reg0\" (period= 2.734 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.532 ns + Longest register register " "Info: + Longest register to register delay is 2.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsq\[0\]~reg0 1 REG LC_X20_Y13_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y13_N2; Fanout = 5; REG Node = 'tsq\[0\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tsq[0]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.443 ns) 0.866 ns tsq\[1\]~126COUT1 2 COMB LC_X20_Y13_N5 2 " "Info: 2: + IC(0.423 ns) + CELL(0.443 ns) = 0.866 ns; Loc. = LC_X20_Y13_N5; Fanout = 2; COMB Node = 'tsq\[1\]~126COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.866 ns" { tsq[0]~reg0 tsq[1]~126COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.928 ns tsq\[2\]~127COUT1 3 COMB LC_X20_Y13_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.928 ns; Loc. = LC_X20_Y13_N6; Fanout = 2; COMB Node = 'tsq\[2\]~127COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[1]~126COUT1 tsq[2]~127COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.990 ns tsq\[3\]~128COUT1 4 COMB LC_X20_Y13_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.990 ns; Loc. = LC_X20_Y13_N7; Fanout = 2; COMB Node = 'tsq\[3\]~128COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[2]~127COUT1 tsq[3]~128COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.052 ns tsq\[4\]~129COUT1 5 COMB LC_X20_Y13_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.052 ns; Loc. = LC_X20_Y13_N8; Fanout = 2; COMB Node = 'tsq\[4\]~129COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[3]~128COUT1 tsq[4]~129COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 1.251 ns tsq\[5\]~130 6 COMB LC_X20_Y13_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.251 ns; Loc. = LC_X20_Y13_N9; Fanout = 6; COMB Node = 'tsq\[5\]~130'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.199 ns" { tsq[4]~129COUT1 tsq[5]~130 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.356 ns tsq\[10\]~135 7 COMB LC_X20_Y12_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.105 ns) = 1.356 ns; Loc. = LC_X20_Y12_N4; Fanout = 6; COMB Node = 'tsq\[10\]~135'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[5]~130 tsq[10]~135 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 1.516 ns tsq\[15\]~140 8 COMB LC_X20_Y12_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.160 ns) = 1.516 ns; Loc. = LC_X20_Y12_N9; Fanout = 6; COMB Node = 'tsq\[15\]~140'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { tsq[10]~135 tsq[15]~140 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.621 ns tsq\[20\]~145 9 COMB LC_X20_Y11_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 1.621 ns; Loc. = LC_X20_Y11_N4; Fanout = 6; COMB Node = 'tsq\[20\]~145'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[15]~140 tsq[20]~145 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 1.781 ns tsq\[25\]~150 10 COMB LC_X20_Y11_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.160 ns) = 1.781 ns; Loc. = LC_X20_Y11_N9; Fanout = 6; COMB Node = 'tsq\[25\]~150'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { tsq[20]~145 tsq[25]~150 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.886 ns tsq\[30\]~155 11 COMB LC_X20_Y10_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.105 ns) = 1.886 ns; Loc. = LC_X20_Y10_N4; Fanout = 1; COMB Node = 'tsq\[30\]~155'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[25]~150 tsq[30]~155 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 2.532 ns tsq\[31\]~reg0 12 REG LC_X20_Y10_N5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.646 ns) = 2.532 ns; Loc. = LC_X20_Y10_N5; Fanout = 2; REG Node = 'tsq\[31\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.646 ns" { tsq[30]~155 tsq[31]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.109 ns ( 83.29 % ) " "Info: Total cell delay = 2.109 ns ( 83.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.423 ns ( 16.71 % ) " "Info: Total interconnect delay = 0.423 ns ( 16.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.532 ns" { tsq[0]~reg0 tsq[1]~126COUT1 tsq[2]~127COUT1 tsq[3]~128COUT1 tsq[4]~129COUT1 tsq[5]~130 tsq[10]~135 tsq[15]~140 tsq[20]~145 tsq[25]~150 tsq[30]~155 tsq[31]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.532 ns" { tsq[0]~reg0 tsq[1]~126COUT1 tsq[2]~127COUT1 tsq[3]~128COUT1 tsq[4]~129COUT1 tsq[5]~130 tsq[10]~135 tsq[15]~140 tsq[20]~145 tsq[25]~150 tsq[30]~155 tsq[31]~reg0 } { 0.000ns 0.423ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.105ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk destination 2.139 ns + Shortest register " "Info: + Shortest clock path from clock \"tclk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns tclk 1 CLK PIN_10 32 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tclk } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns tsq\[31\]~reg0 2 REG LC_X20_Y10_N5 2 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y10_N5; Fanout = 2; REG Node = 'tsq\[31\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { tclk tsq[31]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[31]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[31]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk source 2.139 ns - Longest register " "Info: - Longest clock path from clock \"tclk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns tclk 1 CLK PIN_10 32 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tclk } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns tsq\[0\]~reg0 2 REG LC_X20_Y13_N2 5 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y13_N2; Fanout = 5; REG Node = 'tsq\[0\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { tclk tsq[0]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[0]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[0]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[31]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[31]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[0]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[0]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.532 ns" { tsq[0]~reg0 tsq[1]~126COUT1 tsq[2]~127COUT1 tsq[3]~128COUT1 tsq[4]~129COUT1 tsq[5]~130 tsq[10]~135 tsq[15]~140 tsq[20]~145 tsq[25]~150 tsq[30]~155 tsq[31]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.532 ns" { tsq[0]~reg0 tsq[1]~126COUT1 tsq[2]~127COUT1 tsq[3]~128COUT1 tsq[4]~129COUT1 tsq[5]~130 tsq[10]~135 tsq[15]~140 tsq[20]~145 tsq[25]~150 tsq[30]~155 tsq[31]~reg0 } { 0.000ns 0.423ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.062ns 0.199ns 0.105ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[31]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[31]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[0]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[0]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "tclk tsq\[6\] tsq\[6\]~reg0 6.299 ns register " "Info: tco from clock \"tclk\" to destination pin \"tsq\[6\]\" through register \"tsq\[6\]~reg0\" is 6.299 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk source 2.139 ns + Longest register " "Info: + Longest clock path from clock \"tclk\" to source register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns tclk 1 CLK PIN_10 32 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tclk } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns tsq\[6\]~reg0 2 REG LC_X20_Y12_N0 4 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y12_N0; Fanout = 4; REG Node = 'tsq\[6\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { tclk tsq[6]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[6]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[6]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.987 ns + Longest register pin " "Info: + Longest register to pin delay is 3.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsq\[6\]~reg0 1 REG LC_X20_Y12_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N0; Fanout = 4; REG Node = 'tsq\[6\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tsq[6]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.353 ns) + CELL(1.634 ns) 3.987 ns tsq\[6\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.353 ns) + CELL(1.634 ns) = 3.987 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'tsq\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.987 ns" { tsq[6]~reg0 tsq[6] } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 40.98 % ) " "Info: Total cell delay = 1.634 ns ( 40.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.353 ns ( 59.02 % ) " "Info: Total interconnect delay = 2.353 ns ( 59.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.987 ns" { tsq[6]~reg0 tsq[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.987 ns" { tsq[6]~reg0 tsq[6] } { 0.000ns 2.353ns } { 0.000ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { tclk tsq[6]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.139 ns" { tclk tclk~out0 tsq[6]~reg0 } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.987 ns" { tsq[6]~reg0 tsq[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.987 ns" { tsq[6]~reg0 tsq[6] } { 0.000ns 2.353ns } { 0.000ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:17:44 2008 " "Info: Processing ended: Fri May 09 10:17:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}