tf.fit.qmsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.402 ns register register " "Info: Estimated most critical path is register to register delay of 2.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsq\[0\]~reg0 1 REG LAB_X20_Y13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y13; Fanout = 5; REG Node = 'tsq\[0\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tsq[0]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(0.333 ns) 0.801 ns tsq\[1\]~126COUT1 2 COMB LAB_X20_Y13 2 " "Info: 2: + IC(0.468 ns) + CELL(0.333 ns) = 0.801 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq\[1\]~126COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.801 ns" { tsq[0]~reg0 tsq[1]~126COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.863 ns tsq\[2\]~127COUT1 3 COMB LAB_X20_Y13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.863 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq\[2\]~127COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[1]~126COUT1 tsq[2]~127COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.925 ns tsq\[3\]~128COUT1 4 COMB LAB_X20_Y13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.925 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq\[3\]~128COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[2]~127COUT1 tsq[3]~128COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 0.987 ns tsq\[4\]~129COUT1 5 COMB LAB_X20_Y13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 0.987 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq\[4\]~129COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.062 ns" { tsq[3]~128COUT1 tsq[4]~129COUT1 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.199 ns) 1.186 ns tsq\[5\]~130 6 COMB LAB_X20_Y13 6 " "Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.186 ns; Loc. = LAB_X20_Y13; Fanout = 6; COMB Node = 'tsq\[5\]~130'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.199 ns" { tsq[4]~129COUT1 tsq[5]~130 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.291 ns tsq\[10\]~135 7 COMB LAB_X20_Y12 6 " "Info: 7: + IC(0.000 ns) + CELL(0.105 ns) = 1.291 ns; Loc. = LAB_X20_Y12; Fanout = 6; COMB Node = 'tsq\[10\]~135'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[5]~130 tsq[10]~135 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.396 ns tsq\[15\]~140 8 COMB LAB_X20_Y12 6 " "Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 1.396 ns; Loc. = LAB_X20_Y12; Fanout = 6; COMB Node = 'tsq\[15\]~140'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[10]~135 tsq[15]~140 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.501 ns tsq\[20\]~145 9 COMB LAB_X20_Y11 6 " "Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 1.501 ns; Loc. = LAB_X20_Y11; Fanout = 6; COMB Node = 'tsq\[20\]~145'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[15]~140 tsq[20]~145 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.606 ns tsq\[25\]~150 10 COMB LAB_X20_Y11 6 " "Info: 10: + IC(0.000 ns) + CELL(0.105 ns) = 1.606 ns; Loc. = LAB_X20_Y11; Fanout = 6; COMB Node = 'tsq\[25\]~150'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[20]~145 tsq[25]~150 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.711 ns tsq\[30\]~155 11 COMB LAB_X20_Y10 1 " "Info: 11: + IC(0.000 ns) + CELL(0.105 ns) = 1.711 ns; Loc. = LAB_X20_Y10; Fanout = 1; COMB Node = 'tsq\[30\]~155'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { tsq[25]~150 tsq[30]~155 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.691 ns) 2.402 ns tsq\[31\]~reg0 12 REG LAB_X20_Y10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.691 ns) = 2.402 ns; Loc. = LAB_X20_Y10; Fanout = 2; REG Node = 'tsq\[31\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.691 ns" { tsq[30]~155 tsq[31]~reg0 } "NODE_NAME" } } { "tf.vhd" "" { Text "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.934 ns ( 80.52 % ) " "Info: Total cell delay = 1.934 ns ( 80.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.468 ns ( 19.48 % ) " "Info: Total interconnect delay = 0.468 ns ( 19.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.402 ns" { tsq[0]~reg0 tsq[1]~126COUT1 tsq[2]~127COUT1 tsq[3]~128COUT1 tsq[4]~129COUT1 tsq[5]~130 tsq[10]~135 tsq[15]~140 tsq[20]~145 tsq[25]~150 tsq[30]~155 tsq[31]~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:30:17 2008 " "Info: Processing ended: Fri May 09 10:30:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.fit.smsg " "Info: Generated suppressed messages file D:/altera/70/quartus/work/等精度频率计设计/tf模块/tf.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}