tf.fit.smsg

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri May 09 10:30:14 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off tf -c tf
Info: Automatically selected device EP1C3T100C6 for design tf
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 67 of 67 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 6
    Info: Pin ~ASDO~ is reserved at location 17
Warning: No exact pin location assignment(s) for 35 pins of 35 total pins
    Info: Pin ena not assigned to an exact location on the device
    Info: Pin tsq[0] not assigned to an exact location on the device
    Info: Pin tsq[1] not assigned to an exact location on the device
    Info: Pin tsq[2] not assigned to an exact location on the device
    Info: Pin tsq[3] not assigned to an exact location on the device
    Info: Pin tsq[4] not assigned to an exact location on the device
    Info: Pin tsq[5] not assigned to an exact location on the device
    Info: Pin tsq[6] not assigned to an exact location on the device
    Info: Pin tsq[7] not assigned to an exact location on the device
    Info: Pin tsq[8] not assigned to an exact location on the device
    Info: Pin tsq[9] not assigned to an exact location on the device
    Info: Pin tsq[10] not assigned to an exact location on the device
    Info: Pin tsq[11] not assigned to an exact location on the device
    Info: Pin tsq[12] not assigned to an exact location on the device
    Info: Pin tsq[13] not assigned to an exact location on the device
    Info: Pin tsq[14] not assigned to an exact location on the device
    Info: Pin tsq[15] not assigned to an exact location on the device
    Info: Pin tsq[16] not assigned to an exact location on the device
    Info: Pin tsq[17] not assigned to an exact location on the device
    Info: Pin tsq[18] not assigned to an exact location on the device
    Info: Pin tsq[19] not assigned to an exact location on the device
    Info: Pin tsq[20] not assigned to an exact location on the device
    Info: Pin tsq[21] not assigned to an exact location on the device
    Info: Pin tsq[22] not assigned to an exact location on the device
    Info: Pin tsq[23] not assigned to an exact location on the device
    Info: Pin tsq[24] not assigned to an exact location on the device
    Info: Pin tsq[25] not assigned to an exact location on the device
    Info: Pin tsq[26] not assigned to an exact location on the device
    Info: Pin tsq[27] not assigned to an exact location on the device
    Info: Pin tsq[28] not assigned to an exact location on the device
    Info: Pin tsq[29] not assigned to an exact location on the device
    Info: Pin tsq[30] not assigned to an exact location on the device
    Info: Pin tsq[31] not assigned to an exact location on the device
    Info: Pin tclk not assigned to an exact location on the device
    Info: Pin clr not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "tclk" to use Global clock in PIN 10
Info: Automatically promoted signal "clr" to use Global clock in PIN 66
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 1 input, 32 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.402 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y13; Fanout = 5; REG Node = 'tsq[0]~reg0'
    Info: 2: + IC(0.468 ns) + CELL(0.333 ns) = 0.801 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq[1]~126COUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.863 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq[2]~127COUT1'
    Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.925 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq[3]~128COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 0.987 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'tsq[4]~129COUT1'
    Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.186 ns; Loc. = LAB_X20_Y13; Fanout = 6; COMB Node = 'tsq[5]~130'
    Info: 7: + IC(0.000 ns) + CELL(0.105 ns) = 1.291 ns; Loc. = LAB_X20_Y12; Fanout = 6; COMB Node = 'tsq[10]~135'
    Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 1.396 ns; Loc. = LAB_X20_Y12; Fanout = 6; COMB Node = 'tsq[15]~140'
    Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 1.501 ns; Loc. = LAB_X20_Y11; Fanout = 6; COMB Node = 'tsq[20]~145'
    Info: 10: + IC(0.000 ns) + CELL(0.105 ns) = 1.606 ns; Loc. = LAB_X20_Y11; Fanout = 6; COMB Node = 'tsq[25]~150'
    Info: 11: + IC(0.000 ns) + CELL(0.105 ns) = 1.711 ns; Loc. = LAB_X20_Y10; Fanout = 1; COMB Node = 'tsq[30]~155'
    Info: 12: + IC(0.000 ns) + CELL(0.691 ns) = 2.402 ns; Loc. = LAB_X20_Y10; Fanout = 2; REG Node = 'tsq[31]~reg0'
    Info: Total cell delay = 1.934 ns ( 80.52 % )
    Info: Total interconnect delay = 0.468 ns ( 19.48 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Fri May 09 10:30:17 2008
    Info: Elapsed time: 00:00:03