tf.tan.rpt

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

; N/A   ; None         ; 5.632 ns   ; tsq[11]~reg0 ; tsq[11] ; tclk       ;
; N/A   ; None         ; 5.621 ns   ; tsq[27]~reg0 ; tsq[27] ; tclk       ;
; N/A   ; None         ; 5.615 ns   ; tsq[24]~reg0 ; tsq[24] ; tclk       ;
; N/A   ; None         ; 5.610 ns   ; tsq[23]~reg0 ; tsq[23] ; tclk       ;
; N/A   ; None         ; 5.610 ns   ; tsq[18]~reg0 ; tsq[18] ; tclk       ;
; N/A   ; None         ; 5.569 ns   ; tsq[7]~reg0  ; tsq[7]  ; tclk       ;
; N/A   ; None         ; 5.518 ns   ; tsq[4]~reg0  ; tsq[4]  ; tclk       ;
; N/A   ; None         ; 5.494 ns   ; tsq[17]~reg0 ; tsq[17] ; tclk       ;
; N/A   ; None         ; 5.308 ns   ; tsq[5]~reg0  ; tsq[5]  ; tclk       ;
; N/A   ; None         ; 5.289 ns   ; tsq[30]~reg0 ; tsq[30] ; tclk       ;
; N/A   ; None         ; 5.251 ns   ; tsq[19]~reg0 ; tsq[19] ; tclk       ;
; N/A   ; None         ; 5.211 ns   ; tsq[14]~reg0 ; tsq[14] ; tclk       ;
; N/A   ; None         ; 5.203 ns   ; tsq[8]~reg0  ; tsq[8]  ; tclk       ;
; N/A   ; None         ; 5.172 ns   ; tsq[3]~reg0  ; tsq[3]  ; tclk       ;
; N/A   ; None         ; 4.964 ns   ; tsq[10]~reg0 ; tsq[10] ; tclk       ;
; N/A   ; None         ; 4.928 ns   ; tsq[1]~reg0  ; tsq[1]  ; tclk       ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri May 09 10:17:43 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tf -c tf --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "tclk" is an undefined clock
Info: Clock "tclk" has Internal fmax of 365.76 MHz between source register "tsq[0]~reg0" and destination register "tsq[31]~reg0" (period= 2.734 ns)
    Info: + Longest register to register delay is 2.532 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y13_N2; Fanout = 5; REG Node = 'tsq[0]~reg0'
        Info: 2: + IC(0.423 ns) + CELL(0.443 ns) = 0.866 ns; Loc. = LC_X20_Y13_N5; Fanout = 2; COMB Node = 'tsq[1]~126COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 0.928 ns; Loc. = LC_X20_Y13_N6; Fanout = 2; COMB Node = 'tsq[2]~127COUT1'
        Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 0.990 ns; Loc. = LC_X20_Y13_N7; Fanout = 2; COMB Node = 'tsq[3]~128COUT1'
        Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.052 ns; Loc. = LC_X20_Y13_N8; Fanout = 2; COMB Node = 'tsq[4]~129COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.251 ns; Loc. = LC_X20_Y13_N9; Fanout = 6; COMB Node = 'tsq[5]~130'
        Info: 7: + IC(0.000 ns) + CELL(0.105 ns) = 1.356 ns; Loc. = LC_X20_Y12_N4; Fanout = 6; COMB Node = 'tsq[10]~135'
        Info: 8: + IC(0.000 ns) + CELL(0.160 ns) = 1.516 ns; Loc. = LC_X20_Y12_N9; Fanout = 6; COMB Node = 'tsq[15]~140'
        Info: 9: + IC(0.000 ns) + CELL(0.105 ns) = 1.621 ns; Loc. = LC_X20_Y11_N4; Fanout = 6; COMB Node = 'tsq[20]~145'
        Info: 10: + IC(0.000 ns) + CELL(0.160 ns) = 1.781 ns; Loc. = LC_X20_Y11_N9; Fanout = 6; COMB Node = 'tsq[25]~150'
        Info: 11: + IC(0.000 ns) + CELL(0.105 ns) = 1.886 ns; Loc. = LC_X20_Y10_N4; Fanout = 1; COMB Node = 'tsq[30]~155'
        Info: 12: + IC(0.000 ns) + CELL(0.646 ns) = 2.532 ns; Loc. = LC_X20_Y10_N5; Fanout = 2; REG Node = 'tsq[31]~reg0'
        Info: Total cell delay = 2.109 ns ( 83.29 % )
        Info: Total interconnect delay = 0.423 ns ( 16.71 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "tclk" to destination register is 2.139 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'
            Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y10_N5; Fanout = 2; REG Node = 'tsq[31]~reg0'
            Info: Total cell delay = 1.677 ns ( 78.40 % )
            Info: Total interconnect delay = 0.462 ns ( 21.60 % )
        Info: - Longest clock path from clock "tclk" to source register is 2.139 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'
            Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y13_N2; Fanout = 5; REG Node = 'tsq[0]~reg0'
            Info: Total cell delay = 1.677 ns ( 78.40 % )
            Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "tclk" to destination pin "tsq[6]" through register "tsq[6]~reg0" is 6.299 ns
    Info: + Longest clock path from clock "tclk" to source register is 2.139 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 32; CLK Node = 'tclk'
        Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X20_Y12_N0; Fanout = 4; REG Node = 'tsq[6]~reg0'
        Info: Total cell delay = 1.677 ns ( 78.40 % )
        Info: Total interconnect delay = 0.462 ns ( 21.60 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.987 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N0; Fanout = 4; REG Node = 'tsq[6]~reg0'
        Info: 2: + IC(2.353 ns) + CELL(1.634 ns) = 3.987 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'tsq[6]'
        Info: Total cell delay = 1.634 ns ( 40.98 % )
        Info: Total interconnect delay = 2.353 ns ( 59.02 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Fri May 09 10:17:44 2008
    Info: Elapsed time: 00:00:01