📄 fre_test.map.rpt
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; I/O pins ; 0 ;
; Maximum fan-out node ; CLR ;
; Maximum fan-out ; 65 ;
; Total fan-out ; 480 ;
; Average fan-out ; 3.16 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; |fre_test ; 136 (1) ; 33 ; 0 ; 0 ; 0 ; 103 (0) ; 1 (1) ; 32 (0) ; 62 (0) ; 0 (0) ; |fre_test ;
; |bzq:inst1| ; 63 (63) ; 0 ; 0 ; 0 ; 0 ; 63 (63) ; 0 (0) ; 0 (0) ; 31 (31) ; 0 (0) ; |fre_test|bzq:inst1 ;
; |mux64_8:inst3| ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |fre_test|mux64_8:inst3 ;
; |tf:inst2| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 31 (31) ; 0 (0) ; |fre_test|tf:inst2 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; bzq:inst1|bzq[23] ; inst ; yes ;
; bzq:inst1|bzq[15] ; inst ; yes ;
; bzq:inst1|bzq[7] ; inst ; yes ;
; bzq:inst1|bzq[31] ; inst ; yes ;
; bzq:inst1|bzq[22] ; inst ; yes ;
; bzq:inst1|bzq[14] ; inst ; yes ;
; bzq:inst1|bzq[6] ; inst ; yes ;
; bzq:inst1|bzq[30] ; inst ; yes ;
; bzq:inst1|bzq[21] ; inst ; yes ;
; bzq:inst1|bzq[13] ; inst ; yes ;
; bzq:inst1|bzq[5] ; inst ; yes ;
; bzq:inst1|bzq[29] ; inst ; yes ;
; bzq:inst1|bzq[20] ; inst ; yes ;
; bzq:inst1|bzq[12] ; inst ; yes ;
; bzq:inst1|bzq[4] ; inst ; yes ;
; bzq:inst1|bzq[28] ; inst ; yes ;
; bzq:inst1|bzq[19] ; inst ; yes ;
; bzq:inst1|bzq[11] ; inst ; yes ;
; bzq:inst1|bzq[3] ; inst ; yes ;
; bzq:inst1|bzq[27] ; inst ; yes ;
; bzq:inst1|bzq[18] ; inst ; yes ;
; bzq:inst1|bzq[10] ; inst ; yes ;
; bzq:inst1|bzq[2] ; inst ; yes ;
; bzq:inst1|bzq[26] ; inst ; yes ;
; bzq:inst1|bzq[17] ; inst ; yes ;
; bzq:inst1|bzq[9] ; inst ; yes ;
; bzq:inst1|bzq[1] ; inst ; yes ;
; bzq:inst1|bzq[25] ; inst ; yes ;
; bzq:inst1|bzq[16] ; inst ; yes ;
; bzq:inst1|bzq[8] ; inst ; yes ;
; bzq:inst1|bzq[0] ; inst ; yes ;
; bzq:inst1|bzq[24] ; inst ; yes ;
; Number of user-specified and inferred latches = 32 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 33 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 33 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 8:1 ; 8 bits ; 40 LEs ; 40 LEs ; 0 LEs ; No ; |fre_test|mux64_8:inst3|data[7] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri May 09 10:56:16 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fre_test -c fre_test
Info: Found 1 design units, including 1 entities, in source file fre_test.bdf
Info: Found entity 1: fre_test
Info: Found 2 design units, including 1 entities, in source file mux模块/mux64_8.vhd
Info: Found design unit 1: mux64_8-behav
Info: Found entity 1: mux64_8
Info: Elaborating entity "fre_test" for the top level hierarchy
Info: Elaborating entity "mux64_8" for hierarchy "mux64_8:inst3"
Warning: Using design file bzq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: bzq-behav
Info: Found entity 1: bzq
Info: Elaborating entity "bzq" for hierarchy "bzq:inst1"
Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal "bena" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at bzq.vhd(17): signal "bzq" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at bzq.vhd(13): inferring latch(es) for signal or variable "bzq", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[0]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[1]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[2]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[3]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[4]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[5]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[6]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[7]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[8]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[9]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[10]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[11]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[12]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[13]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[14]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[15]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[16]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[17]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[18]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[19]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[20]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[21]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[22]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[23]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[24]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[25]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[26]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[27]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[28]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[29]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[30]"
Info (10041): Verilog HDL or VHDL info at bzq.vhd(13): inferred latch for "bzq[31]"
Warning: Using design file tf.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: tf-behav
Info: Found entity 1: tf
Info: Elaborating entity "tf" for hierarchy "tf:inst2"
Info: Implemented 152 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 9 output pins
Info: Implemented 136 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Allocated 133 megabytes of memory during processing
Info: Processing ended: Fri May 09 10:56:20 2008
Info: Elapsed time: 00:00:04
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