fre_test.tan.summary

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.353 ns
From           : CL
To             : inst
From Clock     : --
To Clock       : TCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.828 ns
From           : bzq:inst1|bzq[7]
To             : DATA[7]
From Clock     : TCLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.558 ns
From           : SEL[0]
To             : DATA[6]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.664 ns
From           : CLR
To             : bzq:inst1|bzq[1]
From Clock     : --
To Clock       : TCLK
Failed Paths   : 0

Type           : Clock Setup: 'TCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 226.96 MHz ( period = 4.406 ns )
From           : bzq:inst1|bzq[11]
To             : bzq:inst1|bzq[20]
From Clock     : TCLK
To Clock       : TCLK
Failed Paths   : 0

Type           : Clock Hold: 'TCLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : inst
To             : bzq:inst1|bzq[1]
From Clock     : TCLK
To Clock       : TCLK
Failed Paths   : 31

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 31

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