bldcm_con.hier_info

verlog hdl无刷电机控制程序,已在modelsim仿真

|bldcm_con
clk => pwmout~5.IN0
clk => pwmout~4.IN0
clk => pwmout~3.IN0
clk => pwmout~2.IN0
clk => pwmout~1.IN0
clk => pwmout~0.IN0
dir => Decoder3.IN0
hall[0] => Decoder2.IN1
hall[0] => Decoder0.IN1
hall[1] => Decoder1.IN1
hall[1] => Decoder0.IN0
hall[2] => Decoder2.IN0
hall[2] => Decoder1.IN0
pwmout[0] <= pwmout~0.DB_MAX_OUTPUT_PORT_TYPE
pwmout[1] <= pwmout~1.DB_MAX_OUTPUT_PORT_TYPE
pwmout[2] <= pwmout~2.DB_MAX_OUTPUT_PORT_TYPE
pwmout[3] <= pwmout~3.DB_MAX_OUTPUT_PORT_TYPE
pwmout[4] <= pwmout~4.DB_MAX_OUTPUT_PORT_TYPE
pwmout[5] <= pwmout~5.DB_MAX_OUTPUT_PORT_TYPE