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来自「verlog hdl无刷电机控制程序,已在modelsim仿真」· 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity bldcm_con_tb is
    generic(
        CLK_PERIOD      : integer := 2;
        S0              : integer := 0;
        S1              : integer := 4;
        S2              : integer := 6;
        S3              : integer := 7;
        S4              : integer := 3;
        S5              : integer := 1
    );
end bldcm_con_tb;