prev_cmp_bldcm_con.qmsg

verlog hdl无刷电机控制程序,已在modelsim仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 18 20:55:41 2008 " "Info: Processing started: Mon Aug 18 20:55:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bldcm_con -c bldcm_con " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bldcm_con -c bldcm_con" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "bldcm_con.v(16) " "Warning (10261): Verilog HDL Event Control warning at bldcm_con.v(16): Event Control contains a complex event expression" {  } { { "bldcm_con.v" "" { Text "F:/AlterFPGA/BLDCM/bldcm_con.v" 16 0 0 } }  } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"endmodule\";  expecting \"endcase\", or an identifier (\"endmodule\" is a reserved keyword ), or a number, or a system task, or \"(\", or \"\{\", or unary operator bldcm_con.v(58) " "Error (10170): Verilog HDL syntax error at bldcm_con.v(58) near text \"endmodule\";  expecting \"endcase\", or an identifier (\"endmodule\" is a reserved keyword ), or a number, or a system task, or \"(\", or \"\{\", or unary operator" {  } { { "bldcm_con.v" "" { Text "F:/AlterFPGA/BLDCM/bldcm_con.v" 58 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bldcm_con.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file bldcm_con.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Error: Peak virtual memory: 151 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Mon Aug 18 20:55:43 2008 " "Error: Processing ended: Mon Aug 18 20:55:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}