📄 prev_cmp_bldcm_con.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 19 00:39:49 2008 " "Info: Processing started: Tue Aug 19 00:39:49 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off bldcm_con -c bldcm_con --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bldcm_con -c bldcm_con --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk pwmout\[5\] 11.373 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"pwmout\[5\]\" is 11.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 PIN PIN_31 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 6; PIN Node = 'clk'" { } { { "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bldcm_con.v" "" { Text "F:/AlterFPGA/BLDCM/bldcm_con.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.112 ns) + CELL(0.292 ns) 6.873 ns pwmout~195 2 COMB LC_X1_Y4_N9 1 " "Info: 2: + IC(5.112 ns) + CELL(0.292 ns) = 6.873 ns; Loc. = LC_X1_Y4_N9; Fanout = 1; COMB Node = 'pwmout~195'" { } { { "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" "5.404 ns" { clk pwmout~195 } "NODE_NAME" } } { "bldcm_con.v" "" { Text "F:/AlterFPGA/BLDCM/bldcm_con.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.392 ns) + CELL(2.108 ns) 11.373 ns pwmout\[5\] 3 PIN PIN_53 0 " "Info: 3: + IC(2.392 ns) + CELL(2.108 ns) = 11.373 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'pwmout\[5\]'" { } { { "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { pwmout~195 pwmout[5] } "NODE_NAME" } } { "bldcm_con.v" "" { Text "F:/AlterFPGA/BLDCM/bldcm_con.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.869 ns ( 34.02 % ) " "Info: Total cell delay = 3.869 ns ( 34.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.504 ns ( 65.98 % ) " "Info: Total interconnect delay = 7.504 ns ( 65.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera80/quartus/bin/TimingClosureFloorplan.fld" "" "11.373 ns" { clk pwmout~195 pwmout[5] } "NODE_NAME" } } { "d:/altera80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera80/quartus/bin/Technology_Viewer.qrui" "11.373 ns" { clk {} clk~out0 {} pwmout~195 {} pwmout[5] {} } { 0.000ns 0.000ns 5.112ns 2.392ns } { 0.000ns 1.469ns 0.292ns 2.108ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Peak virtual memory: 120 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 19 00:39:50 2008 " "Info: Processing ended: Tue Aug 19 00:39:50 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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