bldcm_con.map.summary

来自「verlog hdl无刷电机控制程序,已在modelsim仿真」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Tue Aug 19 00:39:35 2008
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : bldcm_con
Top-level Entity Name : bldcm_con
Family : Cyclone
Total logic elements : 6
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge