bldcm_con.xml

来自「verlog hdl无刷电机控制程序,已在modelsim仿真」· XML 代码 · 共 11 行

<interfaceDefinition version='1.1' language='verilog' kind='module' name='bldcm_con'>
    <portList>

      <port name='clk' direction='input' type='' kind='' />
      <port name='dir' direction='input' type='' kind='' />
      <port name='hall' direction='input' type='[2:0]' kind='' />
      <port name='pwmout' direction='output' type='[5:0]' kind='regvector' />

    </portList>
</interfaceDefinition>