bldcm_con.fit.rpt

verlog hdl无刷电机控制程序,已在modelsim仿真

+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 6.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 5.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; ASDO,nCSO                                    ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Aug 19 00:39:37 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off bldcm_con -c bldcm_con
Info: Selected device EP1C3T144C8 for design "bldcm_con"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C3T144A8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Warning: No exact pin location assignment(s) for 11 pins of 11 total pins
    Info: Pin pwmout[0] not assigned to an exact location on the device
    Info: Pin pwmout[1] not assigned to an exact location on the device
    Info: Pin pwmout[2] not assigned to an exact location on the device
    Info: Pin pwmout[3] not assigned to an exact location on the device
    Info: Pin pwmout[4] not assigned to an exact location on the device
    Info: Pin pwmout[5] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin dir not assigned to an exact location on the device
    Info: Pin hall[2] not assigned to an exact location on the device
    Info: Pin hall[0] not assigned to an exact location on the device
    Info: Pin hall[1] not assigned to an exact location on the device
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 5 input, 6 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  20 pins available
        Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/AlterFPGA/BLDCM/bldcm_con.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 182 megabytes
    Info: Processing ended: Tue Aug 19 00:39:43 2008
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/AlterFPGA/BLDCM/bldcm_con.fit.smsg.