bldcm_con.tan.rpt

verlog hdl无刷电机控制程序,已在modelsim仿真

Classic Timing Analyzer report for bldcm_con
Tue Aug 19 00:39:49 2008
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 11.373 ns   ; clk  ; pwmout[5] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------+
; tpd                                                               ;
+-------+-------------------+-----------------+---------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To        ;
+-------+-------------------+-----------------+---------+-----------+
; N/A   ; None              ; 11.373 ns       ; clk     ; pwmout[5] ;
; N/A   ; None              ; 11.241 ns       ; hall[2] ; pwmout[3] ;
; N/A   ; None              ; 11.025 ns       ; hall[0] ; pwmout[5] ;
; N/A   ; None              ; 10.862 ns       ; clk     ; pwmout[3] ;
; N/A   ; None              ; 10.764 ns       ; dir     ; pwmout[5] ;
; N/A   ; None              ; 10.758 ns       ; hall[2] ; pwmout[0] ;
; N/A   ; None              ; 10.533 ns       ; clk     ; pwmout[1] ;
; N/A   ; None              ; 10.531 ns       ; clk     ; pwmout[2] ;
; N/A   ; None              ; 10.516 ns       ; hall[0] ; pwmout[3] ;
; N/A   ; None              ; 10.426 ns       ; hall[2] ; pwmout[1] ;
; N/A   ; None              ; 10.373 ns       ; clk     ; pwmout[0] ;
; N/A   ; None              ; 10.362 ns       ; clk     ; pwmout[4] ;
; N/A   ; None              ; 10.267 ns       ; hall[2] ; pwmout[4] ;
; N/A   ; None              ; 10.258 ns       ; dir     ; pwmout[3] ;
; N/A   ; None              ; 10.246 ns       ; dir     ; pwmout[1] ;
; N/A   ; None              ; 10.185 ns       ; hall[0] ; pwmout[2] ;
; N/A   ; None              ; 10.069 ns       ; dir     ; pwmout[4] ;
; N/A   ; None              ; 10.026 ns       ; hall[0] ; pwmout[0] ;
; N/A   ; None              ; 9.926 ns        ; dir     ; pwmout[2] ;
; N/A   ; None              ; 9.762 ns        ; dir     ; pwmout[0] ;
; N/A   ; None              ; 8.297 ns        ; hall[1] ; pwmout[5] ;
; N/A   ; None              ; 7.458 ns        ; hall[1] ; pwmout[1] ;
; N/A   ; None              ; 7.457 ns        ; hall[1] ; pwmout[2] ;
; N/A   ; None              ; 7.297 ns        ; hall[1] ; pwmout[4] ;
+-------+-------------------+-----------------+---------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Aug 19 00:39:49 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bldcm_con -c bldcm_con --timing_analysis_only
Info: Longest tpd from source pin "clk" to destination pin "pwmout[5]" is 11.373 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 6; PIN Node = 'clk'
    Info: 2: + IC(5.112 ns) + CELL(0.292 ns) = 6.873 ns; Loc. = LC_X1_Y4_N9; Fanout = 1; COMB Node = 'pwmout~195'
    Info: 3: + IC(2.392 ns) + CELL(2.108 ns) = 11.373 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'pwmout[5]'
    Info: Total cell delay = 3.869 ns ( 34.02 % )
    Info: Total interconnect delay = 7.504 ns ( 65.98 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 120 megabytes
    Info: Processing ended: Tue Aug 19 00:39:50 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00