bldcm_con.v.bak

verlog hdl无刷电机控制程序,已在modelsim仿真

/*******************************************
              bldcm_con.v
********************************************/
module bldcm_con(
                 //input
                 clk,dir,hall,
                 //output
                 pwmout);
                 
input            clk,dir;
input[2:0]       hall;
output[5:0]      pwmout;
reg[5:0]         pwmreg;
reg[5:0]         pwmout;
reg[5:0]         clkreg;
//reg              hall_mon;

always @(clk)
begin
  clkreg = {6{clk}};
  pwmout = pwmreg&clkreg;
end

always @(hall)
case(dir)
1'b1:
begin
   case(hall)
   3'b000:
   pwmreg <= 6'b100010;
   3'b100:  
   pwmreg <= 6'b100001;  
   3'b110:  
   pwmreg <= 6'b010001;
   3'b111:
   pwmreg <= 6'b010100;
   3'b011:  
   pwmreg <= 6'b001100;  
   3'b001:  
   pwmreg <= 6'b001010;
   default:
   pwmreg <= 6'b000000;
   endcase
end


1'b0:
begin
   case(hall)
   3'b000:
   pwmreg <= 6'b010100;
   3'b100:  
   pwmreg <= 6'b001100;  
   3'b110:  
   pwmreg <= 6'b001010;
   3'b111:
   pwmreg <= 6'b100010;
   3'b011:  
   pwmreg <= 6'b100001;  
   3'b001:  
   pwmreg <= 6'b010001;
   default:
   pwmreg <= 6'b000000;
   endcase

 end
endcase

endmodule