voptwma6kk

来自「verlog hdl无刷电机控制程序,已在modelsim仿真」· 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity bldcm_con is
    port(
        clk             : in     vl_logic;
        dir             : in     vl_logic;
        hall            : in     vl_logic_vector(2 downto 0);
        pwmout          : out    vl_logic_vector(5 downto 0)
    );
end bldcm_con;