_info

verlog hdl无刷电机控制程序,已在modelsim仿真

m255
K3
13
cModel Technology
Z0 dF:\AlterFPGA\BLDCM
T_opt
Z1 VIg84c2Z6k]idMjSOc^MDR3
Z2 04 12 4 work bldcm_con_tb fast 0
Z3 =1-00c09fb57c22-48a99da4-35b-da0
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 OE;O;6.4;39
T_opt1
VK@MVNWQEDc]T2Z4@;n0Ug2
R2
Z6 =1-00c09fb57c22-48a9a51d-2de-ac4
Z7 o-quiet -auto_acc_if_foreign -work work +acc
R5
vbldcm_con
Z8 ILUX0WfV24X4QalI>QFo920
Z9 VaRbC=KLe<5`oPFfKRBfK23
Z10 w1219077398
Z11 8F:/AlterFPGA/BLDCM/bldcm_con.v
Z12 FF:/AlterFPGA/BLDCM/bldcm_con.v
L0 4
Z13 OE;L;6.4;39
r1
31
Z14 o-work work -L mtiAvm -L mtiOvm -L mtiUPF
Z15 !s100 zM?mL;GW^>dQYLQCGROao3
!s85 0
vbldcm_con_tb
Z16 IeAGW]6B0OK[SD:9H=mVLW1
Z17 VzD7`g<FNz@D`:ddMMYFRV3
Z18 w1219076026
Z19 8F:/AlterFPGA/BLDCM/bldcm_con_tb.v
Z20 FF:/AlterFPGA/BLDCM/bldcm_con_tb.v
L0 1
R13
r1
31
R14
Z21 !s100 3UX[jGf77A<EY_MmcOUP?2
!s85 0