📄 sram_2.map.rpt
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; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/deleteme/SRAM_2/SRAM_2.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Thu Jul 27 20:54:08 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAM_2 -c SRAM_2
Info: Found 1 design units, including 1 entities, in source file CLK_10MHZ.v
Info: Found entity 1: CLK_10MHZ
Warning (10273): Verilog HDL warning at SRAM_2.v(81): sign extended using "x" or "z"
Info: Found 1 design units, including 1 entities, in source file SRAM_2.v
Info: Found entity 1: SRAM_2
Info: Elaborating entity "SRAM_2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(44): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(47): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(67): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(68): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(81): truncated value with size 32 to match size of target (16)
Warning (10034): Output port "LEDG[8]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[7]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[6]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[5]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[4]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[3]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[2]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[1]" at SRAM_2.v(28) has no driver
Info: Elaborating entity "CLK_10MHZ" for hierarchy "CLK_10MHZ:M1"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "CLK_10MHZ:M1|altpll:altpll_component"
Info: Duplicate registers merged to single register
Info: Duplicate register "always0~23" merged to single register "always0~0"
Info: Duplicate register "always0~21" merged to single register "always0~0"
Info: Duplicate register "always0~19" merged to single register "always0~0"
Info: Duplicate register "always0~17" merged to single register "always0~0"
Info: Duplicate register "always0~15" merged to single register "always0~0"
Info: Duplicate register "always0~13" merged to single register "always0~0"
Info: Duplicate register "always0~11" merged to single register "always0~0"
Info: Duplicate register "always0~9" merged to single register "always0~0"
Info: Duplicate register "always0~7" merged to single register "always0~0"
Info: Duplicate register "always0~25" merged to single register "always0~0"
Info: Duplicate register "always0~27" merged to single register "always0~0"
Info: Duplicate register "always0~29" merged to single register "always0~0"
Info: Duplicate register "always0~31" merged to single register "always0~0"
Info: Duplicate register "always0~5" merged to single register "always0~0"
Info: Duplicate register "always0~3" merged to single register "always0~0"
Info: Duplicate registers merged to single register
Info: Duplicate register "tmp_data[0]" merged to single register "tmp_addr[0]"
Info: Duplicate register "tmp_data[1]" merged to single register "tmp_addr[1]"
Info: Duplicate registers merged to single register
Info: Duplicate register "tmp_data[2]" merged to single register "tmp_addr[2]"
Info: Duplicate register "tmp_data[3]" merged to single register "tmp_addr[3]"
Info: Duplicate register "tmp_data[4]" merged to single register "tmp_addr[4]"
Info: Duplicate register "tmp_data[5]" merged to single register "tmp_addr[5]"
Info: Duplicate register "tmp_data[6]" merged to single register "tmp_addr[6]"
Info: Duplicate register "tmp_data[7]" merged to single register "tmp_addr[7]"
Info: Duplicate register "tmp_data[8]" merged to single register "tmp_addr[8]"
Info: Duplicate register "tmp_data[9]" merged to single register "tmp_addr[9]"
Info: Duplicate register "tmp_data[10]" merged to single register "tmp_addr[10]"
Info: Duplicate register "tmp_data[11]" merged to single register "tmp_addr[11]"
Info: Duplicate register "tmp_data[12]" merged to single register "tmp_addr[12]"
Info: Duplicate register "tmp_data[13]" merged to single register "tmp_addr[13]"
Info: Duplicate register "tmp_data[14]" merged to single register "tmp_addr[14]"
Info: Duplicate register "tmp_data[15]" merged to single register "tmp_addr[15]"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "LEDG[1]" stuck at GND
Warning: Pin "LEDG[2]" stuck at GND
Warning: Pin "LEDG[3]" stuck at GND
Warning: Pin "LEDG[4]" stuck at GND
Warning: Pin "LEDG[5]" stuck at GND
Warning: Pin "LEDG[6]" stuck at GND
Warning: Pin "LEDG[7]" stuck at GND
Warning: Pin "LEDG[8]" stuck at GND
Warning: Pin "SRAM_CE_N" stuck at GND
Warning: Pin "SRAM_UB_N" stuck at GND
Warning: Pin "SRAM_LB_N" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "KEY[1]"
Info: Implemented 208 device resources after synthesis - the final resource count might be different
Info: Implemented 23 input pins
Info: Implemented 78 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 90 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
Info: Processing ended: Thu Jul 27 20:54:12 2006
Info: Elapsed time: 00:00:04
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