sram_2.tan.summary

来自「使用FPGA控制SRAM的源代码」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.315 ns
From           : KEY[0]
To             : tmp_addr[17]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.799 ns
From           : HEX3[3]~reg0
To             : HEX3[3]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.866 ns
From           : KEY[0]
To             : SRAM_WE_N
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.200 ns
From           : SW[11]
To             : SRAM_ADDR[11]~reg0
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 93.603 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : 156.32 MHz ( period = 6.397 ns )
From           : tmp_addr[1]
To             : tmp_addr[17]
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 0.553 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : tmp_addr[8]
To             : SRAM_DQ[8]~reg0
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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