📄 sram_2.tan.rpt
字号:
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; ; PLL output ; 10.0 MHz ; 0.000 ns ; 0.000 ns ; CLOCK_50 ; 1 ; 5 ; -2.358 ns ; ;
; CLOCK_50 ; ; User Pin ; 50.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0' ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 93.603 ns ; 156.32 MHz ( period = 6.397 ns ) ; tmp_addr[1] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 6.184 ns ;
; 93.660 ns ; 157.73 MHz ( period = 6.340 ns ) ; tmp_addr[0] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 6.127 ns ;
; 93.762 ns ; 160.31 MHz ( period = 6.238 ns ) ; tmp_addr[1] ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 6.025 ns ;
; 93.793 ns ; 161.11 MHz ( period = 6.207 ns ) ; tmp_addr[12] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.786 ns ; 5.993 ns ;
; 93.812 ns ; 161.60 MHz ( period = 6.188 ns ) ; tmp_addr[3] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.975 ns ;
; 93.819 ns ; 161.79 MHz ( period = 6.181 ns ) ; tmp_addr[0] ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.968 ns ;
; 93.833 ns ; 162.15 MHz ( period = 6.167 ns ) ; tmp_addr[1] ; tmp_addr[15] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.954 ns ;
; 93.890 ns ; 163.67 MHz ( period = 6.110 ns ) ; tmp_addr[0] ; tmp_addr[15] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.897 ns ;
; 93.904 ns ; 164.04 MHz ( period = 6.096 ns ) ; tmp_addr[1] ; tmp_addr[14] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.883 ns ;
; 93.930 ns ; 164.74 MHz ( period = 6.070 ns ) ; tmp_addr[2] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.857 ns ;
; 93.952 ns ; 165.34 MHz ( period = 6.048 ns ) ; tmp_addr[12] ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.786 ns ; 5.834 ns ;
; 93.952 ns ; 165.34 MHz ( period = 6.048 ns ) ; tmp_addr[14] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.786 ns ; 5.834 ns ;
; 93.953 ns ; 165.37 MHz ( period = 6.047 ns ) ; tmp_addr[8] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.834 ns ;
; 93.961 ns ; 165.59 MHz ( period = 6.039 ns ) ; tmp_addr[0] ; tmp_addr[14] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.826 ns ;
; 93.971 ns ; 165.86 MHz ( period = 6.029 ns ) ; tmp_addr[3] ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.816 ns ;
; 93.975 ns ; 165.98 MHz ( period = 6.025 ns ) ; tmp_addr[1] ; tmp_addr[13] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns ; 99.787 ns ; 5.812 ns ;
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