_primary.vhd

来自「VHDL语言实现PWM信号」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity pwm_gen is
    port(
        clk             : in     vl_logic;
        duty_cycle      : in     vl_logic_vector(3 downto 0);
        pwm             : out    vl_logic
    );
end pwm_gen;