_primary.vhd

来自「VHDL语言实现PWM信号」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity clkgen is
    port(
        osc             : in     vl_logic;
        pwm_clk         : out    vl_logic;
        dc_clk          : out    vl_logic
    );
end clkgen;